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SST89C58 Datasheet

  • SST89C58

  • FlashFlex51 MCU

  • 367.69KB

  • SST   SST

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FlashFlex51 MCU
SST89C54 / SST89C58
Preliminary Specifications
EA# = 1 & SFCF[7] = 1
FFFFh
F000h
EFFFh
4 KByte
INTERNAL
(Block 1)
EA# = 1 & SFCF[7] = 0
FFFFh
FFFFh
EA# = 0
32 KByte
EXTERNAL
28 KByte
EXTERNAL
64 KByte
EXTERNAL
8000h
7FFFh
8000h
7FFFh
32 KByte
INTERNAL
(Block 0)
32 KByte
INTERNAL
(Block 0)
0000h
0000h
0000h
344 ILL F11.1
F
IGURE
6: SST89C58 P
ROGRAM
M
EMORY
O
RGANIZATION
Memory Re-mapping
The SST89C54/58 memory re-mapping feature allows
users to reorganize internal Flash memory sectors so
that interrupts may be serviced when Block 0 of the
internal Flash is being programmed. Since Block 0
occupies the low order program address space of the
8051 architecture where the interrupt vectors reside,
those interrupt vectors will normally not be available
when Block 0 is being programmed.
SST89C54/58 provides four options of Memory Re-
mapping (Refer to Table 2). When the lowest 4 KBytes
are remapped, any program access within logical ad-
dress range 0000h 鈥?0FFFh will have the 4 most signifi-
cant address bits forced to 鈥?鈥? redirecting the access to
F000h 鈥?FFFFh. Note that the physical contents of the
re-mapped portion of Block 0 (i.e. physical locations
0000h 鈥?0FFFh in the current example) will not be
accessible. Block 1 will still also be accessible through
F000h 鈥?FFFFh. Figures 7 and 8 show re-mapped
program memory organization for the SST89C54/58.
漏 2000 Silicon Storage Technology, Inc.
10
344-2 8/00

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