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SST89C58 Datasheet

  • SST89C58

  • FlashFlex51 MCU

  • 367.69KB

  • SST   SST

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FlashFlex51 MCU
SST89C54 / SST89C58
Preliminary Specifications
NOTES:
1. Capacitive loading on Ports 0 & 2 may cause spurious noise to be superimposed on the V
OL
s of ALE and Ports 1 & 3. The noise due to
external bus capacitance discharging into the Port 0 & 2 pins when the pins make 1 -to- 0 transitions during bus operations. In the worst
cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify ALE
with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input.
2. Capacitive loading on Ports 0 & 2 may cause the V
OH
on ALE and PSEN# to momentarily fall below the V
DD
- 0.7 specification when the
address bits are stabilizing.
3. Pins of Ports 1, 2 & 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
maximum value when Vin is approximately 2V.
4. Load capacitance for Port 0, ALE & PSEN#= 100pF, load capacitance for all other outputs= 80pF.
5. Under steady state (non-transient) conditions, I
OL
must be externally limited as follows:
Maximum I
OL
per port pin:
15mA
26mA
Maximum I
OL
per 8-bit port:
Maximum I
OL
total for all outputs:
71mA
If I
OL
exceeds the test condition, V
OH
may exceed the related specification. Pins are not guaranteed to sink current greater than the listed
test conditions.
6. Pin capacitance is characterized but not tested. EA# is 25pF (max).
7. See Figures 22, 23, 24 and 25 for test conditions. Minimum V
DD
for Power Down is 2.7V.
VDD
IDD
VDD
1
2
3
4
5
VDD
VDD
RST
8XC5X
CLOCK
SIGNAL
(NC)
XTAL2
XTAL1
VSS
P0
EA#
VDD
VDD
P0
RST
8XC5X
CLOCK
SIGNAL
(NC)
XTAL2
XTAL1
VSS
EA#
IDD
VDD
6
7
8
344 ILL F26.0
344 ILL F24.0
All other pins disconnected
All other pins disconnected
9
10
11
12
13
14
F
IGURE
22: I
DD
T
EST
C
ONDITION
, A
CTIVE
M
ODE
F
IGURE
23: I
DD
T
EST
C
ONDITION
, I
DLE
M
ODE
VDD = 3 or 5V
VDD
P0
RST
8XC5X
(NC)
XTAL2
XTAL1
VSS
EA#
VDD
IDD
VDD
VDD = 5V
VDD
P0
RST
8XC5X
(NC)
XTAL2
XTAL1
VSS
EA#
VDD
IDD
VDD
344 ILL F25.2
344 ILL F33.3
All other pins disconnected
All other pins disconnected
15
F
IGURE
25: I
DD
T
EST
C
ONDITION
, S
TANDBY
(S
TOP
C
LOCK
)
M
ODE
F
IGURE
24: I
DD
T
EST
C
ONDITION
, P
OWER
D
OWN
M
ODE
16
漏 2000 Silicon Storage Technology, Inc.
41
344-2 8/00

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