MSM80C154S Datasheet

  • MSM80C154S

  • USER'S MANUAL

  • 1946.50KB

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隆 Semiconductor
(3) External data memory access AC characteristics
MSM80C154S/83C154S
V
CC
=2.2 to 6.0V, V
SS
=0V, Ta=鈥?0掳C to +85掳C
PORT 0, ALE, and
PSEN
connected with 100pF load, other connected with 80pF load
Variable clock from*1
Parameter
XTAL1, XTAL2 Oscillator Cycle
ALE Signal Width
Address Setup Time
(to ALE Falling Edge)
Address Hold Time
(from ALE Falling Edge)
RD
Signal Width
WR
Signal Width
RAM Data Read Time
(from
RD
Signal Falling Edge)
RAM Data Read Hold Time
(from
RD
Signal Rising Edge)
Data Bus Floating Time
(from
RD
Signal Rising Edge)
RAM Data Read Time
(from ALE Signal Falling Edge)
RAM Data Read Time
(from Address Output)
RD/WR
Output Time from ALE
Falling Edge
RD/WR
Output Time from Address
Output
WR
Output Time from Data Output
Time from Data to
WR
Rising Edge
Data Hold Time
(from
WR
Rising Edge)
Time from to Address Float
RD
Output
Time from
RD/WR
Rising Edge to
ALE Rising Edge
Symbol
Min.
t
CLCL
t
LHLL
t
AVLL
t
LLAX
t
RLRL
t
WLWH
t
RLDV
t
RHDX
t
RHDZ
t
LLDV
t
AVDV
t
LLWL
t
AVWL
t
QVWX
t
QVWH
t
WHQX
t
RLAZ
t
WHLH
41.7
2t
CLCL
-40
1t
CLCL
-15
1t
CLCL
-35
6t
CLCL
-100
6t
CLCL
-100
鈥?/div>
0
鈥?/div>
鈥?/div>
鈥?/div>
3t
CLCL
-40
*2
3t
CLCL
-100
4t
CLCL
-70
1t
CLCL
-40
7t
CLCL
-105
2t
CLCL
-50
0
1t
CLCL
-30
1 to 24 MHz
Max.
1000
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
5t
CLCL
-105
鈥?/div>
2t
CLCL
-70
8t
CLCL
-100
9t
CLCL
-105
3t
CLCL
+40
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
1t
CLCL
+40
*2
1t
CLCL
+100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
*1 The variable check is from 0 to 24 MHz when the external check is used.
*2 For 2.2拢V
CC
<4 V
31/40

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