MAX1545 Datasheet_PDF文件下载_芯片资料查询

Dual-Phase, Quick-PWM Controllers for

Programmable CPU Core Power Supplies

MAX1519/MAX1545

SUS

1 LSB PER R

TIME

CYCLE

V

DAC

OUTPUT SET BY SUS AND S0鈥揝1

OUTPUT SET BY D0鈥揇4

t

SLEW

TIME

CLOCK

t

BLANK

= 24 CLKS

t

SLEW

t

BLANK

= 24 CLKS

VROK

VROK BLANKING

Figure 4. Suspend Transition

than the current limit set by ILIM. The transition time is

given by:

t

SLEW

鈮?/div>

t

SLEW

鈮?/div>

铮?/div>

V

OLD

鈭?/div>

V

NEW

铮?/div>

for V

OUT

rising

f

SLEW

铮?/div>

V

LSB

铮?/div>

1

铮＋

V

OLD

鈭?/div>

V

NEW

铮?/div>

铮，

铮?+

2

铮?/div>

for V

OUT

falling

f

SLEW

铮帮－

V

LSB

铮?/div>

where f

SLEW

= 500kHz

鉁?/div>

30k鈩?/ R

TIME

, V

OLD

is the

original DAC setting, V

NEW

is the new DAC setting, and

V

LSB

is the DAC鈥檚 smallest voltage increment. The

additional two clock cycles on the falling edge time are

due to internal synchronization delays. See TIME

Frequency Accuracy in the

Electrical Characteristics

for

f

SLEW

limits.

The practical range of R

TIME

is 15k鈩?to 150k鈩?corre-

sponding to 1.0碌s to 10碌s per 25mV step. Although the

DAC takes discrete steps, the output filter makes the

transitions relatively smooth. The average inductor cur-

rent required to make an output voltage transition is:

I

L

鈮?/div>

C

OUT

脳

V

LSB

脳

f

SLEW

an overvoltage fault. During normal forced-PWM opera-

tion (SKIP = high), the controller detects an OVP fault if

the output voltage exceeds the set DAC voltage by

more than 13% (min). During pulse-skipping operation

(SKIP = REF or GND), the controller detects an OVP

fault if the output voltage exceeds the fixed 2V (typ)

threshold. When the OVP circuit detects an overvoltage

fault, it immediately sets the fault latch, pulls VROK low,

and activates the shutdown sequence.

This action discharges the output filter capacitor and

forces the output to ground. If the condition that caused

the overvoltage (such as a shorted high-side MOSFET)

persists, the battery fuse blows. The controller remains

shut down until the fault latch is cleared by toggling

SHDN

or cycling the V

CC

power supply below 1V. OVP

is ignored during output voltage transitions and remains

blanked for an additional 24 clock cycles after the con-

troller reaches the final DAC code value.

Overvoltage protection can be disabled through the

鈥渘o- fault鈥?test mode (see the

No-Fault Test Mode

sec-

tion).

Output Undervoltage Shutdown

The output UVP function is similar to foldback current

limiting, but employs a timer rather than a variable current

limit. If the MAX1519/MAX1545 output voltage is under

70% of the nominal value, the controller activates the

shutdown sequence and sets the fault latch.

Once the controller ramps down to the 0V DAC code

setting, it forces the DL_ low-side gate-driver high, and

pulls the DH_ high-side gate-driver low. Toggle

SHDN

Fault Protection

Output Overvoltage Protection

(MAX1545 Only)

The overvoltage protection (OVP) circuit is designed to

protect the CPU against a shorted high-side MOSFET by

drawing high current and blowing the battery fuse. The

MAX1519/MAX1545 continuously monitor the output for

22

______________________________________________________________________________________

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