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MAX1545数据手册封面

MAX1545 Datasheet

  • MAX1545

  • dual-phase, Quick-PWM™, step-down controllers

  • 813.95KB

  • Maxim   Maxim

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Dual-Phase, Quick-PWM Controllers for
Programmable CPU Core Power Supplies
MAX1519/MAX1545
Table 5. Suspend Mode DAC Codes
LOWER SUSPEND CODES
SUS*
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
S1
GND
GND
GND
GND
REF
REF
REF
REF
OPEN
OPEN
OPEN
OPEN
V
CC
V
CC
V
CC
V
CC
S0
GND
REF
OPEN
V
CC
GND
REF
OPEN
V
CC
GND
REF
OPEN
V
CC
GND
REF
OPEN
V
CC
OUTPUT
VOLTAGE
(V)
0.675
0.700
0.725
0.750
0.775
0.800
0.825
0.850
0.875
0.900
0.925
0.950
0.975
1.000
1.025
1.050
SUS*
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
UPPER SUSPEND CODES
S1
GND
GND
GND
GND
REF
REF
REF
REF
OPEN
OPEN
OPEN
OPEN
V
CC
V
CC
V
CC
V
CC
S0
GND
REF
OPEN
V
CC
GND
REF
OPEN
V
CC
GND
REF
OPEN
V
CC
GND
REF
OPEN
V
CC
OUTPUT
VOLTAGE
(V)
1.075
1.100
1.125
1.150
1.175
1.200
1.225
1.250
1.275
1.300
1.325
1.350
1.375
1.400
1.425
1.450
*Connect
the three-level SUS input to a 2.7V or greater supply (3.3V or V
CC
) for an input logic level high.
Thermal-Fault Protection
The MAX1519/MAX1545 feature a thermal fault-protec-
tion circuit. When the junction temperature rises above
+160掳C, a thermal sensor activates the fault latch and
activates the soft-shutdown sequence. Once the con-
troller ramps down to the 0V DAC code setting, it forces
the DL_ low-side gate-driver high, and pulls the DH_
high-side gate-driver low. Toggle
SHDN
or cycle the
V
CC
power supply below 1V to clear the fault latch and
reactivate the controller after the junction temperature
cools by 15掳C.
Thermal shutdown can be disabled through the 鈥渘o-fault鈥?/div>
test mode (see the
No-Fault Test Mode
section).
No-Fault Test Mode
The latched-fault protection features and overlap mode
can complicate the process of debugging prototype
breadboards since there are (at most) a few milliseconds
in which to determine what went wrong. Therefore, a 鈥渘o-
fault鈥?test mode is provided to disable the fault protection
(overvoltage protection, undervoltage protection, and
thermal shutdown) and overlap mode. Additionally, the
test mode clears the fault latch if it has been set. The no-
fault test mode is entered by forcing 12V to 15V
on
SHDN.
24
Multiphase Quick-PWM
5V Bias Supply (V
CC
and V
DD
)
The Quick-PWM controller requires an external 5V bias
supply in addition to the battery. Typically, this 5V bias
supply is the notebook鈥檚 95%-efficient 5V system sup-
ply. Keeping the bias supply external to the IC
improves efficiency and eliminates the cost associated
with the 5V linear regulator that would otherwise be
needed to supply the PWM circuit and gate drivers. If
stand-alone capability is needed, the 5V bias supply
can be generated with an external linear regulator.
The 5V bias supply must provide V
CC
(PWM controller)
and V
DD
(gate-drive power), so the maximum current
drawn is:
I
BIAS
= I
CC
+ f
SW
(Q
G(LOW)
+ Q
G(HIGH)
)
where I
CC
is provided in the
Electrical Characteristics,
f
SW
is the switching frequency, and Q
G(LOW)
and Q
G(HIGH)
are the MOSFET data sheet鈥檚 total gate-charge specifi-
cation limits at V
GS
= 5V. V+ and V
DD
can be tied
together if the input power source is a fixed 4.5V to 5.5V
supply. If the 5V bias supply is powered up prior to the
battery supply, the enable signal (SHDN going from low
to high) must be delayed until the battery voltage is pre-
sent to ensure startup.
______________________________________________________________________________________

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