MAX1545 Datasheet_PDF文件下载_芯片资料查询

Dual-Phase, Quick-PWM Controllers for

Programmable CPU Core Power Supplies

phase, the peak inductor currents of each phase are

staggered, resulting in lower output ripple voltage by

reducing the total inductor ripple current. For multi-

phase operation, the maximum ESR to meet ripple

requirements is:

R

ESR

鈮?/div>

V

RIPPLE

铮?/div>

V

IN

鈭?/div>

V

OUT

铮?铮?/div>

V

OUT

铮?/div>

V

OUT

铮?/div>

畏

TOTAL

铮?/div>

铮?铮?/div>

V

铮?鈭?畏

SLAVE

(

畏

SLAVE

鈭?/div>

1)

铮?/div>

L

铮?/div>

t

TRIG

铮?/div>

f

SW

L

铮?/div>

铮?铮?/div>

IN

铮?/div>

between the output capacitors and sense resistors.

For a standard 300kHz application, the ESR zero frequen-

cy must be well below 95kHz, preferably below 50kHz.

Tantalum, Sanyo POSCAP, and Panasonic SP capacitors

in widespread use at the time of publication have typical

ESR zero frequencies below 50kHz. For example, the

ESR needed to support a 30mV

P-P

ripple in a 40A design

is 30mV/(40A

脳

0.3) = 2.5m鈩? Four 330碌F/2.5V Panasonic

SP (type XR) capacitors in parallel provide 2.5m鈩?(max)

ESR. Their typical combined ESR results in a zero at

40kHz.

Ceramic capacitors have a high ESR zero frequency,

but applications with significant voltage positioning can

take advantage of their size and low ESR. Do not put

high-value ceramic capacitors directly across the out-

put without verifying that the circuit contains enough

voltage positioning and series PC board resistance to

ensure stability. When only using ceramic output

capacitors, output overshoot (V

SOAR

) typically deter-

mines the minimum output capacitance requirement.

Their relatively low capacitance value can cause output

overshoot when stepping from full-load to no-load con-

ditions, unless a small inductor value is used (high

switching frequency) to minimize the energy transferred

from inductor to capacitor during load-step recovery.

The efficiency penalty for operating at 550kHz is about

5% when compared to the 300kHz circuit, primarily due

to the high-side MOSFET switching losses.

Unstable operation manifests itself in two related but

distinctly different ways: double-pulsing and feedback

loop instability. Double-pulsing occurs due to noise on

the output or because the ESR is so low that there is

not enough voltage ramp in the output voltage signal.

This 鈥渇ools鈥?the error comparator into triggering a new

cycle immediately after the minimum off-time period

has expired. Double-pulsing is more annoying than

harmful, resulting in nothing worse than increased out-

put ripple. However, it can indicate the possible pres-

ence of loop instability due to insufficient ESR. Loop

instability can result in oscillations at the output after

line or load steps. Such perturbations are usually

damped, but can cause the output voltage to rise

above or fall below the tolerance limits.

The easiest method for checking stability is to apply a

very fast zero-to-max load transient and carefully

observe the output voltage ripple envelope for over-

shoot and ringing. It can help to simultaneously monitor

the inductor current with an AC current probe. Do not

allow more than one cycle of ringing after the initial

step-response under/overshoot.

MAX1519/MAX1545

where

畏

TOTAL

is the total number of active phases,

畏

SLAVE

is the total number of slave phases (triggered

phases), f

SW

is the switching frequency per phase, and

t

TRIG

is the trigger delay between the master鈥檚 DH ris-

ing edge and the slave鈥檚 DH rising edge. The trigger

delay must be less than 1/(f

SW

脳畏

TOTAL

) for stable

operation. The actual capacitance value required

relates to the physical size needed to achieve low ESR,

as well as to the chemistry of the capacitor technology.

Thus, the capacitor is usually selected by ESR and volt-

age rating rather than by capacitance value (this is true

of polymer types).

When using low-capacity ceramic filter capacitors,

capacitor size is usually determined by the capacity

needed to prevent V

SAG

and V

SOAR

from causing

problems during load transients. Generally, once

enough capacitance is added to meet the overshoot

requirement, undershoot at the rising load edge is no

longer a problem (see the V

SAG

and V

SOAR

equations

in the

Transient Response

section).

Output Capacitor Stability Considerations

For Quick-PWM controllers, stability is determined by

the value of the ESR zero relative to the switching fre-

quency. The boundary of instability is given by the fol-

lowing equation:

f

ESR

鈮?/div>

where:

f

ESR

=

and:

R

EFF

=

R

ESR

+

A

VPS

R

SENSE

+

R

PCB

where C

OUT

is the total output capacitance, R

ESR

is the

total equivalent-series resistance, R

SENSE

is the cur-

rent-sense resistance, A

VPS

is the voltage-positioning

gain, and R

PCB

is the parasitic board resistance

1

2蟺R

EFF

C

OUT

f

SW

蟺

______________________________________________________________________________________

33

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