Dual-Phase, Quick-PWM Controllers for
Programmable CPU Core Power Supplies
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V+ = 15V, V
CC
= V
DD
= V
SHDN
= V
TON
= V
SKIP
= V
S0
= V
S1
= V
CODE
= 5V, V
FB
= V
CMP
= V
CMN
= V
CSP
= V
CSN
= 1.3V, OFS = SUS = GNDS = D0鈥揇4 = GND;
T
A
= 0掳C to +85掳C,
unless otherwise specified. Typical values are at T
A
= +25掳C.)
PARAMETER
GATE DRIVERS
DH_ Gate-Driver On-Resistance
DL_ Gate-Driver On-Resistance
DH_ Gate-Driver Source/Sink
Current
DL_ Gate-Driver Sink Current
DL_ Gate-Driver Source Current
Dead Time
VOLTAGE-POSITIONING AMPLIFIER
Input Offset Voltage
Input Bias Current
Op Amp Disable Threshold
Common-Mode Input Voltage
Range
Common-Mode Rejection Ratio
Power-Supply Rejection Ratio
Large-Signal Voltage Gain
Output Voltage Swing
Input Capacitance
Gain-Bandwidth Product
Slew Rate
Capacitive-Load Stability
LOGIC AND I/O
SHDN
Input High Voltage
SHDN
Input Low Voltage
SHDN
No-Fault Threshold
Three-Level Input Logic Levels
Logic Input Current
D0鈥揇4 Logic Input High Voltage
D0鈥揇4 Logic Input Low Voltage
V
IH
V
IL
V
SHDN
High
SUS,
SKIP
SHDN,
SUS,
SKIP
REF
Low
-1
1.6
0.8
12
2.7
1.2
2.3
0.8
+1
碌A
V
V
V
0.8
0.4
15
V
V
V
No sustained oscillations
V
OS
I
BIAS
V
OAIN-
V
CM
CMRR
PSRR
A
OA
Guaranteed by CMRR test
V
OAIN+
= V
OAIN-
= 0 to 2.5V
V
CC
= 4.5V to 5.5V
R
L
= 1k鈩?to V
CC
/2
|V
OAIN+
- V
OAIN-
|
鈮?/div>
10mV,
R
L
= 1k鈩?to V
CC
/2
V
CC
- V
FBH
V
FBL
OAIN+, OAIN-
3
0
70
75
80
115
100
112
77
47
11
3
0.3
400
300
200
-1
0.1
V
CC
- 1
+1
200
V
CC
-
0.4
2.5
mV
nA
V
V
dB
dB
dB
mV
pF
MHz
V/碌s
pF
R
ON(DH)
R
ON(DL)
I
DH
I
DL(SINK)
BST_ - LX_ forced to 5V
High state (pullup)
Low start (pulldown)
DH_ forced to 2.5V,
BST_ - LX_ forced to 5V
DL_ forced to 5V
DL_ rising
DH_ rising
1.0
1.0
0.4
1.6
4
1.6
35
26
4.5
4.5
2
鈩?/div>
鈩?/div>
A
A
A
ns
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MAX1519/MAX1545
I
DL(SOURCE)
DL_ forced to 2.5V
t
DEAD
_______________________________________________________________________________________
5
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