Freescale Semiconductor, Inc.
back high after the transaction, before another rising edge of SCPCLK is encountered. Note that
SCP Rx is ignored during the time that SCP Tx is being driven. Also note that SCP Tx comes out
of high impedance only when it is transmitting data.
SCPEN
SCPCLK
DON鈥橳 CARE
SCP Rx
R/W
A2
A1
A0
DON鈥橳 CARE
Freescale Semiconductor, Inc...
SCP Tx
D3
D2 D1
D0
HIGH IMPEDANCE
Figure 5鈥?. Serial Control Port Nibble Register Read Operation
5.2.2
SCP Nibble Register Write
A nibble register write is an 8鈥揵it SCP transaction. Figure 5鈥? illustrates this process. To initiate an
SCP nibble register write, the SCPEN pin must be brought low. Following this, an R/W bit followed
by three primary address bits are shifted (MSB first) into an intermediate buffer register on the first
four rising edges of SCPCLK following the high鈥搕o鈥搇ow transition of SCPEN. If a write operation is
to be performed, then R/W should be a 0. The three address bits, clocked in after the R/W bit, select
the nibble register to be written to. The data shifted in on the next four rising edges of SCPCLK is
then written to the selected register. Throughout this whole operation the SCP Tx pin remains in high鈥?/div>
impedance state. Note that if a selected register or bit in a selected register is 鈥渞ead only鈥? then a
write operation has no effect.
SCPEN
SCPCLK
SCP Rx
DON鈥橳 CARE
R/W A2
A1
A0
D3
D2
D1
D0
DON鈥橳 CARE
SCP Tx
HIGH IMPEDANCE
NOTES:
1. R/W = 0 for a read operation.
2. Data is shifted out on SCP Tx on the falling edges of SCPCLK, MSB first.
3. Data is shifted into the chip from SCP Rx on the rising edges of SCPCLK, MSB first.
4. A2, A1, A0 = 0 to 6.
Figure 5鈥?. Serial Control Port Nibble Register Write Operation
5鈥?
MC145574
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