MC145574 Datasheet

  • MC145574

  • ISDN S/T-Interface Transceiver

  • 658.40KB

  • Motorola   Motorola

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Freescale Semiconductor, Inc.
8.3
NR1
This register is a read only register and can be reset by application of either a hardware or software
reset. A per鈥揵it description of nibble register 1 (NR1) follows.
b3
NR1
Activation Indication
b2
Error Indication
b1
NT: Not Applicable
TE: Multiframing
Detection
ro
ro
b0
Frame Sync
ro
ro
Freescale Semiconductor, Inc...
NR1(3) 鈥?Activation Indication (AI)
This bit is set by the MC145574 when the loop is fully activated. Thus, when the MC145574 is config-
ured as an NT, this bit is set when it is transmitting INFO 4 and receiving INFO 3. Conversely, when
the MC145574 is configured as a TE, this bit is set when it is transmitting INFO 3 and receiving INFO
4. Note that NR1(3) is a read only bit.
NR1(2) 鈥?Error Indication (EI)
NR1(2) is set by the MC145574 S/T transceiver to indicate an error condition has been detected by
the activation state machine of the transceiver, as outlined in CCITT I.430, ETSI ETS 300012, and
ANSI T1.605. The low鈥搕o鈥揾igh level transition of the EI bit corresponds to the EI1 error indication
reporting, while the high鈥搕o鈥搇ow level transition of the EI bit corresponds to the EI2 error indication
reporting recovery. Note that NR1(2) is a read only bit.
NR1(1) 鈥?NT: Not Applicable
TE: Multiframing Detection (MD)
In the TE mode of operation, this bit is set by the MC145574 S/T transceiver whenever it detects
multiframing from the NT. This bit will be set low if multiframing synchronization is lost and will return
high when synchronization is re鈥揳cquired. This bit applies only to TE鈥揷onfigured devices. Note that
NR1(1) is a read only bit.
NR1(0) 鈥?Frame Sync (FS)
NR1(0) is set high by the MC145574 S/T transceiver when frame synchronization is achieved. NR1(0)
is reset by the MC145574 whenever frame synchronization is lost. Note that NR1(0) is a read only
bit.
8.4
NR2
This register is a read/write register and can be cleared by application of either a hardware or software
reset. A per鈥揵it description of nibble register 2 (NR2) is as follows.
b3
NR2
Activation Request
rw
b2
NT: Deactivate Request
TE: Not Applicable
rw
b1
Activation Timer
Expired
rw
b0
NT: NT Terminal Class
TE: Class
rw
NR2(3) 鈥?Activation Request (AR)
When NR2(3) is set to 1, an activation request input is passed to the activate state machine within
the MC145574 S/T transceiver, as outlined in CCITT I.430, ETSI ETS 300012, and ANSI T1.605.
If the transceiver is in the idle state (i.e., transmitting and receiving INFO 0) and is configured as an
NT, then AR causes INFO 2 to be sent out on the transmit side of the S/T鈥搃nterface. Alternatively,
if the chip is configured as a TE and is in the idle state, then writing a 1 to NR2(3) causes INFO 1
to be sent out. Note that this bit will be returned low by the MC145574 S/T transceiver after its active
MOTOROLA
MC145574
For More Information On This Product,
Go to: www.freescale.com
8鈥?

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