Freescale Semiconductor, Inc.
OVERLAY REGISTER MAP DEFINITION
10
10.1
INTRODUCTION
There are eleven overlay registers (OR0 through OR9 and OR15) in the MC145574. The overlay regis-
ters are a second bank of registers available when the overlay register control bit BR15(7) is set to
a logic 1. These overlay registers are in the IDL2 TSA mode used to assign the timeslot used by each
channel (B1, B2, and D) for transmission and reception; OR0 through OR5, OR6, OR7, and OR8
are control registers used in the GCI indirect mode, and OR15 gives the revision number of the S/T
chip.
Freescale Semiconductor, Inc...
Table 10鈥?. Overlay Register Map
(7)
OR0
OR1
OR2
OR3
OR4
OR5
OR5
OR6
OR7
TSA B1
Enable
Disable
3V
Regulator
Reserved
(6)
(5)
(4)
(3)
(2)
(1)
(0)
Din B1 Channel Timeslot Bits (7:0) (IDL2 Mode)
Din B2 Channel Timeslot Bits (7:0) (IDL2 Mode)
Din D Channel Timeslot Bits (7:0) (IDL2 Mode)
Dout B1 Channel Timeslot Bits (7:0) (IDL2 Mode)
Dout B2 Channel Timeslot Bits (7:0) (IDL2 Mode)
Dout D Channel Timeslot Bits (7:0) (IDL2 Mode)
Time Slot Assignment for GCI Mode
TSA B2
Enable
Enable
S/G Bit
TSA D
Enable
Enable
TCLK
Disable XTAL
Dual Frame
Syncs
TE Mode
Enable
Dout Open
Drain
Long
Frame
Master Mode
Enable
S2
GCI Indirect
Mode Enable
8/10 Bit
Select
FIX Enable
Force
INFO 2
Transmission
Overlay
Register
Enable
Rev 5
Rev 4
Rev 3
Rev 2
S1
CLK1
TSEN B1/B2
Enable,
BCL Enable
NT Terminal
Mode Enable
T3F8
Enable
Rev 1
S0
CLK0
TSEN
D Channel
Enable
Sleep
Enable
T3F6
Disable
Rev 0
OR8
OR9
OR15
MOTOROLA
MC145574
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10鈥?