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MC145574数据手册封面

MC145574 Datasheet

  • MC145574

  • ISDN S/T-Interface Transceiver

  • 658.40KB

  • Motorola   Motorola

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Freescale Semiconductor, Inc.
10.5
OR3
(7)
OR3
(6)
(5)
(4)
(3)
(2)
(1)
(0)
Dout B1 Channel Timeslot Bits (7:0)
OR3(7:0) 鈥?Rx B1 Channel Timeslot
This register allows the B1 channel timeslot output from the Dout pin to be allocated 1 of 256 start
points, corresponding to each 2鈥揵it boundary defined by the CLK. The timeslot can be either 8 or
10 CLKs wide. The default value for OR3 is 00H.
10.6
OR4
(7)
OR4
(6)
(5)
(4)
(3)
(2)
(1)
(0)
Freescale Semiconductor, Inc...
Dout B2 Channel Timeslot Bits (7:0)
OR4(7:0) 鈥?Rx B2 Channel Timeslot
This register allows the B2 channel timeslot output from the Dout pin to be allocated 1 of 256 start
points, corresponding to each 2鈥揵it boundary defined by the CLK. The timeslot can be either 8 or
10 CLKs wide. The default value for OR4 is 04H.
10.7
OR5
(7)
OR5
OR5
(6)
(5)
(4)
(3)
(2)
(1)
(0)
Dout D Channel Timeslot Bits (7:0)
(GCI Indirect Mode)
S2
S1
S0
OR5(7:0) 鈥?Rx D Channel Timeslot
This register allows the D channel timeslot output from the Dout pin to be allocated 1 of 256 start points,
corresponding to each 2鈥揵it boundary defined by the CLK. The default value for OR5 is 08H.
OR5(2:0) 鈥?GCI Timeslot, S(2:0)
In GCI indirect mode, control of the GCI timeslot is available through the S(2:0) bits. S(2:0)=0H is
the initialized state, timeslot 0. The timeslot selected must be compatible with the GCI DCL clock rate
being used; i.e., if the clock rate is 2048 kHz, only the first four timeslots are available. Bits 7:3 must
be programmed as 0.
Table 10鈥?. S(2:0) GCI Timeslot
Assignment
S2
0
0
0
0
1
1
1
1
S1
0
0
1
1
0
0
1
1
S0
0
1
0
1
0
1
0
1
Timeslot
0
1
2
3
4
5
6
7
MOTOROLA
MC145574
For More Information On This Product,
Go to: www.freescale.com
10鈥?

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