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MC9S12DG128B Datasheet

  • MC9S12DG128B

  • Users Guide

  • 3857.74KB

  • Motorola   Motorola

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MC9S12DT128B Device User Guide 鈥?V01.07
A.1.5 Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima
is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the
device.
This device contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (e.g., either V
SS5
or V
DD5
).
Table A-1 Absolute Maximum Ratings
1
Num
1
2
3
4
5
6
7
8
9
10
11
12
13
Rating
I/O, Regulator and Analog Supply Voltage
Digital Logic Supply Voltage
2
PLL Supply Voltage
2
Voltage difference VDDX to VDDR and VDDA
Voltage difference VSSX to VSSR and VSSA
Digital I/O Input Voltage
Analog Reference
XFC, EXTAL, XTAL inputs
TEST input
Instantaneous Maximum Current
Single pin limit for all digital I/O pins
3
Instantaneous Maximum Current
Single pin limit for XFC, EXTAL, XTAL
4
Instantaneous Maximum Current
Single pin limit for TEST
5
Storage Temperature Range
Symbol
V
DD5
V
DD
V
DDPLL
鈭?/div>
VDDX
鈭?/div>
VSSX
V
IN
V
RH,
V
RL
V
ILV
V
TEST
I
D
I
Min
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-25
-25
-0.25
鈥?65
Max
6.0
3.0
3.0
0.3
0.3
6.0
6.0
3.0
10.0
+25
+25
0
155
Unit
V
V
V
V
V
V
V
V
V
mA
mA
mA
掳C
DL
I
DT
T
stg
NOTES:
1. Beyond absolute maximum ratings device might be damaged.
2. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply.
The absolute maximum ratings apply when the device is powered from an external source.
3. All digital I/O pins are internally clamped to V
SSX
and V
DDX
, V
SSR
and V
DDR
or V
SSA
and V
DDA
.
4. Those pins are internally clamped to V
SSPLL
and V
DDPLL
.
5. This pin is clamped low to V
SSPLL
, but not clamped high. This pin must be tied low in applications.
A.1.6 ESD Protection and Latch-up Immunity
All ESD testing is in conformity with CDF-AEC-Q100 Stress test qualification for Automotive Grade
Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body
Model (HBM), the Machine Model (MM) and the Charge Device Model.
85

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