鈮?/div>
V
DDA
.
This constraint exists since the sample buffer amplifier can not drive
beyond the power supply levels that it ties to. If the input level goes outside of this range it will effectively
be clipped.
Table A-8 ATD Operating Characteristics
Conditions are shown in
Table A-4
unless otherwise noted
Num C
Reference Potential
1
2
3
4
D
Rating
Low
High
Symbol
V
RL
V
RH
V
RH
-V
RL
f
ATDCLK
Min
V
SSA
V
DDA
/2
4.50
0.5
14
7
12
6
Typ
Max
V
DDA
/2
V
DDA
Unit
V
V
V
MHz
Cycles
碌s
Cycles
碌s
碌s
mA
mA
C Differential Reference Voltage
1
D ATD Clock Frequency
ATD 10-Bit Conversion Period
D
5.00
5.25
2.0
28
14
26
13
20
0.75
0.375
Clock Cycles
2
N
CONV10
Conv, Time at 2.0MHz ATD Clock f
ATDCLK
T
CONV10
ATD 8-Bit Conversion Period
Clock Cycles
(2)
Conv, Time at 2.0MHz ATD Clock f
ATDCLK
5
D
N
CONV8
T
CONV8
t
SR
I
REF
I
REF
6
7
8
D Stop Recovery Time (V
DDA
=5.0 Volts)
P Reference Supply current (Both ATD modules on)
P Reference Supply current (Only one ATD module on)
NOTES:
1. Full accuracy is not guaranteed when differential voltage is less than 4.50V
2. The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample
period of 16 ATD clocks.
A.2.2 Factors influencing accuracy
Three factors 鈥?source resistance, source capacitance and current injection 鈥?have an influence on the
accuracy of the ATD.
A.2.2.1 Source Resistance:
Due to the input pin leakage current as specified in
Table A-6
in conjunction with the source resistance
there will be a voltage drop from the signal source to the ATD input. The maximum source resistance R
S
93