P87C552 Datasheet

IC型号：
P87C552
PDF描述：
80C51 8-bit microcontroller
文件大小：
393.52KB
芯片厂家：
Philips

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Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller

8K/256 OTP, 8 channel 10 bit A/D, I

C, PWM,

capture/compare, high I/O, low voltage (2.7V鈥?.5V), low power

P87C552

SIO1, I

C Serial I/O:

The I

C bus uses two wires (SDA and SCL) to

transfer information between devices connected to the bus. The

main features of the bus are:

鈥?Bidirectional data transfer between masters and slaves

鈥?Multimaster bus (no central master)

鈥?Arbitration between simultaneously transmitting masters without

corruption of serial data on the bus

鈥?Serial clock synchronization allows devices with different bit rates

to communicate via one serial bus

鈥?Serial clock synchronization can be used as a handshake

mechanism to suspend and resume serial transfer

鈥?The I

C bus may be used for test and diagnostic purposes

The output latches of P1.6 and P1.7 must be set to logic 1 in order

to enable SIO1.

The 8XC552 on-chip

logic provides a serial interface that meets

the I

C bus specification and supports all transfer modes (other than

the low-speed mode) from and to the I

C bus. The SIO1 logic

handles bytes transfer autonomously. It also keeps track of serial

transfers, and a status register (S1STA) reflects the status of SIO1

and the I

C bus.

The CPU interfaces to the I

C logic via the following four special

function registers: S1CON (SIO1 control register), S1STA (SIO1

status register), S1DAT (SIO1 data register), and S1ADR (SIO1

slave address register). The SIO1 logic interfaces to the external I

bus via two port 1 pins: P1.6/SCL (serial clock line) and P1.7/SDA

(serial data line).

A typical I

C bus configuration is shown in Figure 32, and Figure 33

shows how a data transfer is accomplished on the bus. Depending

on the state of the direction bit (R/W), two types of data transfers are

possible on the I

C bus:

1. Data transfer from a master transmitter to a slave receiver. The

first byte transmitted by the master is the slave address. Next

follows a number of data bytes. The slave returns an

acknowledge bit after each received byte.

2. Data transfer from a slave transmitter to a master receiver. The

first byte (the slave address) is transmitted by the master. The

slave then returns an acknowledge bit. Next follows the data

bytes transmitted by the slave to the master. The master returns

an acknowledge bit after all received bytes other than the last

byte. At the end of the last received byte, a 鈥渘ot acknowledge鈥?is

returned.

The master device generates all of the serial clock pulses and the

START and STOP conditions. A transfer is ended with a STOP

condition or with a repeated START condition. Since a repeated

START condition is also the beginning of the next serial transfer, the

C bus will not be released.

Modes of Operation:

The on-chip SIO1 logic may operate in the

following four modes:

1. Master Transmitter Mode:

Serial data output through P1.7/SDA while P1.6/SCL outputs the

serial clock. The first byte transmitted contains the slave address

of the receiving device (7 bits) and the data direction bit. In this

case the data direction bit (R/W) will be logic 0, and we say that

a 鈥淲鈥?is transmitted. Thus the first byte transmitted is SLA+W.

Serial data is transmitted 8 bits at a time. After each byte is

transmitted, an acknowledge bit is received. START and STOP

conditions are output to indicate the beginning and the end of a

serial transfer.

2. Master Receiver Mode:

The first byte transmitted contains the slave address of the

transmitting device (7 bits) and the data direction bit. In this case

the data direction bit (R/W) will be logic 1, and we say that an 鈥淩鈥?/div>

is transmitted. Thus the first byte transmitted is SLA+R. Serial

data is received via P1.7/SDA while P1.6/SCL outputs the serial

clock. Serial data is received 8 bits at a time. After each byte is

received, an acknowledge bit is transmitted. START and STOP

conditions are output to indicate the beginning and end of a

serial transfer.

3. Slave Receiver Mode:

Serial data and the serial clock are received through P1.7/SDA

and P1.6/SCL. After each byte is received, an acknowledge bit is

transmitted. START and STOP conditions are recognized as the

beginning and end of a serial transfer. Address recognition is

performed by hardware after reception of the slave address and

direction bit.

4. Slave Transmitter Mode:

The first byte is received and handled as in the slave receiver

mode. However, in this mode, the direction bit will indicate that

the transfer direction is reversed. Serial data is transmitted via

P1.7/SDA while the serial clock is input through P1.6/SCL.

START and STOP conditions are recognized as the beginning

and end of a serial transfer.

In a given application, SIO1 may operate as a master and as a

slave. In the slave mode, the SIO1 hardware looks for its own slave

address and the general call address. If one of these addresses is

detected, an interrupt is requested. When the microcontroller wishes

to become the bus master, the hardware waits until the bus is free

before the master mode is entered so that a possible slave action is

not interrupted. If bus arbitration is lost in the master mode, SIO1

switches to the slave mode immediately and can detect its own

slave address in the same serial transfer.

1999 Mar 30

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