Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I
2
C, PWM,
capture/compare, high I/O, low voltage (2.7V鈥?.5V), low power
P87C552
AC ELECTRICAL CHARACTERISTICS
(Continued)
SYMBOL
PARAMETER
INPUT
OUTPUT
I
2
C Interface (Refer to Figure 55)
5
t
HD;STA
t
LOW
t
HIGH
t
RC
t
FC
t
SU;DAT1
t
SU;DAT2
t
SU;DAT3
t
HD;DAT
t
SU;STA
t
SU;STO
t
BUF
t
RD
START condition hold time
SCL low time
SCL high time
SCL rise time
SCL fall time
Data set-up time
SDA set-up time (before rep. START cond.)
SDA set-up time (before STOP cond.)
Data hold time
Repeated START set-up time
STOP condition set-up time
Bus free time
SDA rise time
鈮?/div>
14 t
CLCL
鈮?/div>
16 t
CLCL
鈮?/div>
14 t
CLCL
鈮?/div>
1碌s
鈮?/div>
0.3碌s
鈮?/div>
250ns
鈮?/div>
250ns
鈮?/div>
250ns
鈮?/div>
0ns
鈮?/div>
14 t
CLCL
鈮?/div>
14 t
CLCL
鈮?/div>
14 t
CLCL
鈮?/div>
1碌s
> 4.0碌s
1
> 4.7碌s
1
> 4.0碌s
1
鈥?/div>
2
< 0.3碌s
3
> 20 t
CLCL
鈥?t
RD
> 1碌s
1
> 8 t
CLCL
> 8 t
CLCL
鈥?t
FC
> 4.7碌s
1
> 4.0碌s
1
> 4.7碌s
1
鈥?/div>
2
t
FD
SDA fall time
鈮?/div>
0.3碌s
< 0.3碌s
3
NOTES:
1. At 100 kbit/s. At other bit rates this value is inversely proportional to the bit-rate of 100 kbit/s.
2. Determined by the external bus-line capacitance and the external bus-line pull-resistor, this must be < 1碌s.
3. Spikes on the SDA and SCL lines with a duration of less than 3 t
CLCL
will be filtered out. Maximum capacitance on bus-lines SDA and
SCL = 400pF.
4. t
CLCL
= 1/f
OSC
= one oscillator clock period at pin XTAL1. For 62ns (42s) < t
CLCL
< 285ns (16MHz > f
OSC
> 3.5MHz) the SI01 interface
meets the I
2
C-bus specification for bit-rates up to 100 kbit/s.
5. These values are guaranteed but not 100% production tested.
1999 Mar 30
66
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