Figure 58. I
2. Idle Mode:
a. The following pins must be forced to V
: Port 0 and EW.
b. The following pins must be forced to V
ref鈥?/div>
, and EA.
c. Ports 1.6 and 1.7 should be connected to V
DD
through resistors of sufficiently high value such that the sink current into these pins
cannot exceed the I
OL1
spec of these pins. These pins must not have logic 0 written to them prior to this measurement.
d. The following pins must be disconnected: XTAL2 and all pins not specified above.
V
DD
鈥?.5
0.5V
0.7V
DD
0.2V
DD
鈥?.1
t
CHCL
t
CLCX
t
CLCL
t
CHCX
t
CLCH
SU00220
Figure 59. Clock Signal Waveform for I
DD
Tests in Active and Idle Modes
t
CLCH
= t
CHCL
= 5ns
V
DD
P1.6
P1.7
RST
STADC
P0
V
DD
I
DD
V
DD
V
DD
(NC)
XTAL2
XTAL1
V
SS
EW
EA
AV
SS
AV
ref鈥?/div>
SU00221
Figure 60. I
DD
Test Condition, Power Down Mode
All other pins are disconnected. V
DD
= 2V to 5.5V
3
3. Power Down Mode:
a. The following pins must be forced to V
DD
: Port 0 and EW.
b. The following pins must be forced to V
SS
: RST, STADC, XTAL1, AV
ss
, AV
ref鈥?/div>
, and EA.
c. Ports 1.6 and 1.7 should be connected to V
DD
through resistors of sufficiently high value such that the sink current into these pins
cannot exceed the I
OL1
spec of these pins. These pins must not have logic 0 written to them prior to this measurement.
d. The following pins must be disconnected: XTAL2 and all pins not specified above.
1999 Mar 30
71
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