DS2751
Figure 12. 1-WIRE CRC GENERATION BLOCK DIAGRAM
INPUT
MSb
XOR
XOR
LSb
XOR
HARDWARE CONFIGURATION
Because the 1-Wire bus has only a single line, it is important that each device on the bus be able to drive
it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must connect to the
bus with open-drain or tri-state output drivers. The DS2751 uses an open-drain output driver as part of the
bidirectional interface circuitry shown in Figure 13. If a bidirectional pin is not available on the bus
master, separate output, and input pins can be connected together.
The 1-Wire bus must have a pullup resistor at the bus-master end of the bus. For short line lengths, the
value of this resistor should be approximately 5kW. The idle state for the 1-Wire bus is high. If, for any
reason, a bus transaction must be suspended, the bus must be left in the idle state in order to properly
resume the transaction later. If the bus is left low for more than 120
m
s, slave devices on the bus begin to
interpret the low period as a reset pulse, effectively terminating the transaction.
Figure 13. 1-WIRE BUS INTERFACE CIRCUITRY
BUS MASTER
V
PULLUP
(2.0V to 5.5V)
4.7kW
Rx
1mA
Typ.
Rx = RECEIVE
Tx = TRANSMIT
100W
MOSFET
Rx
DS2751 1-WIRE PORT
Tx
Tx
TRANSACTION SEQUENCE
The protocol for accessing the DS2751 through the 1-Wire port is as follows:
搂
搂
搂
搂
Initialization
Net Address Command
Function Command
Transaction/Data
The sections that follow describe each of these steps in detail.
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