DS2751
All transactions of the 1-Wire bus begin with an initialization sequence consisting of a reset pulse
transmitted by the bus master followed by a presence pulse simultaneously transmitted by the DS2751
and any other slaves on the bus. The presence pulse tells the bus master that one or more devices are on
the bus and ready to operate. For more details, see the
I/O Signaling
section.
NET ADDRESS COMMANDS
Once the bus master has detected the presence of one or more slaves, it can issue one of the net address
commands described in the following paragraphs. The name of each ROM command is followed by the
8-bit opcode for that command in square brackets. Figure 14 presents a transaction flowchart of the net
address commands.
Read Net Address [33h or 39h].
This command allows the bus master to read the DS2751鈥檚 1-Wire net
address. This command can only be used if there is a single slave on the bus. If more than one slave is
present, a data collision occurs when all slaves try to transmit at the same time (open drain produces a
wired-AND result). The RNAOP bit in the Status Register selects the opcode for this command, with
RNAOP = 0 indicating 33h and RNAOP = 1 indicating 39h.
Match Net Address [55h].
This command allows the bus master to specifically address one DS2751 on
the 1-Wire bus. Only the addressed DS2751 responds to any subsequent function command. All other
slave devices ignore the function command and wait for a reset pulse. This command can be used with
one or more slave devices on the bus.
Skip Net Address [CCh].
This command saves time when there is only one DS2751 on the bus by
allowing the bus master to issue a function command without specifying the address of the slave. If more
than one slave device is present on the bus, a subsequent function command can cause a data collision
when all slaves transmit data at the same time.
Search Net Address [F0h].
This command allows the bus master to use a process of elimination to
identify the 1-Wire net addresses of all slave devices on the bus. The search process involves the
repetition of a simple three-step routine: read a bit, read the complement of the bit, then write the desired
value of that bit. The bus master performs this simple three-step routine on each bit location of the net
address. After one complete pass through all 64 bits, the bus master knows the address of one device. The
remaining devices can then be identified on additional iterations of the process. See Chapter 5 of the
Book
of DS19xx iButton
庐
Standards
for a comprehensive discussion of a net address search, including an actual
example. This publication can be found on the Maxim/Dallas website at
www.maxim-ic.com.
FUNCTION COMMANDS
After successfully completing one of the net address commands, the bus master can access the features of
the DS2751 with any of the function commands described in the following paragraphs. The name of each
function is followed by the 8-bit opcode for that command in square brackets.
Read Data [69h, XX].
This command reads data from the DS2751 starting at memory address XX. The
LSb of the data in address XX is available to be read immediately after the MSb of the address has been
entered. Because the address is automatically incremented after the MSb of each byte is received, the LSb
of the data at address XX + 1 is available to be read immediately after the MSb of the data at address XX.
If the bus master continues to read beyond address FFh, the DS2751 outputs logic 1 until a reset pulse
occurs. Addresses labeled 鈥渞eserved鈥?in the memory map contain undefined data. The Read Data
command can be terminated by the bus master with a reset pulse at any bit boundary.
iButton is a registered trademark of Dallas Semiconductor.
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