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IDT77301 Datasheet

  • IDT77301

  • DEMULTIPLEXER-FIFO

  • 342.79KB

  • IDT

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IDT77301
UtopiaFIFO鈩?1 to 4 (128 x 9 x 4) Demultiplexer-FIFO
Commercial and Industrial Temperature Ranges
Pin Description
Symbol
1-2, 4-8,
10, 100
Name
DATA-b
I/O
O
Description
Data bus output for FIFO-b. Master Mode with BNE HIGH: output is a 9-bit word. Master Mode with
BNE LOW: data bus output is a data nibble (Q0-Q3); Q4-Q6 data lines unused; data out Q7 is an
output enable control signal to the slave device; Q8 is an output of bit 9/18 valid during the low and
high nibble transfer. Slave Mode with BNE LOW: data bus output is a data nibble (Q0-Q3); Q4-Q7
lines unused; Q8 is an output of D8/D17 valid during the low and high nibble transfer.
Start Of Cell (FIFO-b). Output from UtopiaFIFO. Active on first byte of data transfer. SOCS deasserts
for all remaining byte transfers.
Cell Available (FIFO-b). CLAVS notifies the UtopiaFIFO port a cell transfer can be initiated by the port.
Enable (FIFO-b). Master Mode:
ENS
is an active low output. When asserted, a data transfer will take
place on the current clock cycle. Slave Mode:
ENS
is an input which causes the fifo port to update a
data nibble (Q0-3) on the output bus on the next read clock edge.
Data bus output for FIFO-c. Master Mode with BNE HIGH: output is a 9-bit word. Master Mode with
BNE LOW: data bus output is a data nibble (Q0-Q-3); Q4-Q6 data lines unused; data out Q7 is an
output enable control signal to the slave device; Q8 is an output of bit 9/18 valid during the low and
high nibble transfer. Slave Mode with BNE LOW: data bus output is a data nibble (Q1-Q3); Q4-Q7
lines unused; Q8 is an output of D8/D17 valid during the low and high nibble transfer.
Start Of Cell (FIFO-c). Output from UtopiaFIFO. Active on first byte of data transfer. SOCS deasserts
for all remaining byte transfers.
Cell Available (FIFO-c) CLAVS notifies the UtopiaFIFO port a cell transfer can be initiated by the port.
Enable (FIFO-c). Master Mode:
ENS
is an active low output. When asserted, a data transfer will take
place on the current clock cycle. Slave Mode:
ENS
is an input which causes the fifo port to update a
data nibble (Q0-3) on the output bus on the next read clock edge.
Data bus output for FIFO-d. Master Mode with BNE HIGH: output is a 9-bit word. Master Mode with
BNE LOW: data bus output is a data nibble (Q0-Q3); Q4-Q6 data lines unused; data out Q7 is an
output enable control signal to the slave device; Q8 is an output of bit 9/18 valid during the low and
high nibble transfer. Slave Mode with BNE LOW; data bus output is a data nibble (Q0-Q3); Q4-Q7
lines unused; Q8 is an output of D8/D17 valid during the low and high nibble transfer.
Start Of Cell (FIFO-d). Output from UtopiaFIFO. Active on first byte of data transfer. SOCS deasserts
for all remaining byte transfers.
Cell Available (FIFO-d). CLAVS notifies the UtopiaFIFO port a cell transfer can be initiated by the port.
Enable (FIFO-d). Master Mode:
ENS
is an active low output. When asserted, a data transfer will take
place on the current clock cycle. Slave Mode:
ENS
is an input which causes the fifo port to update a
data nibble (Q0-3) on the output bus on the next read clock edge.
Input port write enable. Each data write requires
ENR
assertion.
Input port Cell space Available. Notifies the controlling agent the FIFO(s) selected by the address
bus can accept a complete cell.
Input port Start of Cell. Assertion: first work is currently on bus.
BSS low (18-Bit bus): Data bus input Data 11-Data 17
BSS high (9-bit bus): Input port for loading programmable registers.
3240 tbl 01
11
12
13
SOCS-b
CLAVS-b
O
I
I/O
ENS
-b
14, 16-20,
22-24
DATA-c
O
25
26
28
SOCS-c
CLAVS-c
O
I
I/O
ENS
-c
29-32,
34-38
DATA-d
O
40
41
42
SOCS-d
CLAVS-d
O
I
I/O
ENS
-d
43
44
46
47-53
ENR
CLAVR
SOCR
Data 17-11/
P_CS 6-0
I
O
I
I
3

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