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IDT72205LB Datasheet

  • IDT72205LB

  • CMOS SyncFIFO?

  • 181.80KB

  • IDT

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IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO鈩?/div>
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
Commercial And Industrial Temperature Ranges
OPERATING CONFIGURATIONS
SINGLE DEVICE CONFIGURATION
A single IDT72205LB/72215LB/72225LB/72235LB/72245LB
may be used when the application requirements are for 256/
512/1,024/2,048/4,096 words or less. These FIFOs are in a
single Device Configuration when the First Load (
FL
), Write
Expansion In (
WXI
) and Read Expansion In (
RXI
) control inputs
are grounded (Figure 19).
RESET (
WRITE CLOCK (WCLK)
WRITE ENABLE (
LOAD (
)
IDT
72205LB
72215LB
72225LB
72235LB
72245LB
)
)
)
)
READ CLOCK (RCLK)
READ ENABLE (
OUTPUT ENABLE (
DATA OUT (Q
0
- Q
17
)
EMPTY FLAG (
)
)
)
)
DATA IN (D
0
- D
17
)
FULL FLAG (
)
PROGRAMMABLE (
HALF-FULL FLAG (
PROGRAMMABLE (
FIRST LOAD (
)
)
READ EXPANSION IN (
WRITE EXPANSION IN (
)
2766 drw 21
Figure 19. Block Diagram of Single 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, 4,096 x 18 Synchronous FIFO
WIDTH EXPANSION CONFIGURATION
Word width may be increased simply by connecting together
the control signals of multiple devices. Status flags can be
detected from any one device. The exceptions are the Empty
Flag and Full Flag. Because of variations in skew between
RCLK and WCLK, it is possible for flag assertion and deassertion
to vary by one cycle between FIFOs. To avoid problems the
RESET (
)
user must create composite flags by ANDing the Empty Flags
of every FIFO, and separately ANDing all Full Flags. Figure 20
demonstrates a 36-word width by using two IDT72205B/72215B/
72225B/72235B/72245Bs. Any word width can be attained by
adding additional IDT72205B/72215B/72225B/72235B/
72245Bs. Please see the Application Note AN-83.
RESET (
)
DATA IN (D) 36
18
18
READ CLOCK (RCLK)
READ ENABLE (
OUTPUT ENABLE (
)
72205LB
72215LB
72225LB
72235LB
72245LB
72205LB
72215LB
72225LB
72235LB
72245LB
PROGRAMMABLE (
)
)
)
WRITE CLOCK (WCLK)
WRITE ENABLE (
LOAD (
)
)
PROGRAMMABLE (
HALF FULL FLAG (
)
EMPTY FLAG (
)
FULL FLAG (
)
18
FIRST LOAD ( )
WRITE EXPANSION IN (
READ EXPANSION IN (
18
DATA OUT (Q)
36
)
)
2766 drw 22
NOTE:
1. Do not connect any output control signals directly together.
Figure 20. Block Diagram of 256 x 36, 512 x 36, 1,024 x 36, 2,048 x 36, 4,096 x 36
Synchronous FIFO Memory Used in a Width Expansion Configuration
14

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