鈭?/div>
0: Serial data on the serial port 0 is read from or written to this location. It actually
consists of two separate internal 8-bit registers. One is the receive resister, and the
other is the transmit buffer. Any read access gets data from the receive data buffer,
while write access is to the transmit data buffer.
P4.2 Base Address Low Byte Register
Bit:
7
A7
Mnemonic: P42AL
6
A6
5
A5
4
A4
3
A3
2
A2
Address: 9Ah
1
A1
0
A0
P4.2 Base Address High Byte Register
Bit:
7
A15
Mnemonic: P42AH
6
A14
5
A13
4
A12
3
A11
2
A10
Address: 9Bh
1
A9
0
A8
P4.3 Base Address Low Byte Register
Bit:
7
A7
Mnemonic: P43AL
6
A6
5
A5
4
A4
3
A3
2
A2
Address: 9Ch
1
A1
0
A0
P4.3 Base Address High Byte Register
Bit:
7
A15
Mnemonic: P43AH
6
A14
5
A13
4
A12
3
A11
2
A10
Address: 9Dh
1
A9
0
A8
ISP Control Register
Bit:
7
SWRST/HWB
Mnemonic: CHPCON
6
-
5
LDAP
4
-
3
-
2
-
1
LDSEL
0
ENP
Address: 9Fh
SWRST/HWB: Set this bit to launch a whole device reset that is same as asserting high to RST pin,
micro controller will be back to initial state and clear this bit automatically. To read
this bit, its alternate function to indicate the ISP hardware reboot mode is invoking
when read it in high.
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