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W77E516数据手册封面

W77E516 Datasheet

  • W77E516

  • uC-Based Consumer IC > Controller IC > 8-Bit Microcontrolle...

  • 1107.54KB

  • Winbond

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Preliminary W77E516
EA: Global enable. Enable/disable all interrupts except for PFI.
ES1: Enable Serial Port 1 interrupt.
ET2: Enable Timer 2 interrupt.
ES: Enable Serial Port 0 interrupt.
ET1: Enable Timer 1 interrupt
EX1: Enable external interrupt 1
ET0: Enable Timer 0 interrupt
EX0: Enable external interrupt 0
Slave Address
Bit:
7
6
5
4
3
2
1
0
Mnemonic: SADDR
Address: A9h
SADDR: The SADDR should be programmed to the given or broadcast address for serial port 0 to
which the slave processor is designated.
Slave Address 1
Bit:
7
6
5
4
3
2
1
0
Mnemonic: SADDR1
Address: AAh
SADDR1: The SADDR1 should be programmed to the given or broadcast address for serial port 1
to which the slave processor is designated.
ISP Address Low Byte
Bit:
7
A7
Mnemonic: SFRAL
6
A6
5
A5
4
A4
3
A3
2
A2
1
A1
Address: ACh
0
A0
Low byte destination address for In System Programming operations. SFRAH and SFRAL address
a specific ROM bytes for erasure, porgramming or read.
ISP Address High Byte
Bit:
7
A15
Mnemonic: SFRAH
6
A14
5
A13
4
A12
3
A11
2
A10
1
A9
Address: ADh
0
A8
High byte destination address for In System Programming operations. SFRAH and SFRAL address
a specific ROM bytes for erasure, porgramming or read.
- 22 -

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