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W77E516数据手册封面

W77E516 Datasheet

  • W77E516

  • uC-Based Consumer IC > Controller IC > 8-Bit Microcontrolle...

  • 1107.54KB

  • Winbond

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Preliminary W77E516
Continued
MXT freq. (Hz)
22.6M
鈭?/div>
25M
25.1M
鈭?/div>
27.5M
27.6M
鈭?/div>
30M
30.1M
鈭?/div>
32.5M
32.6M
鈭?/div>
35M
35.1M
鈭?/div>
37.5M
37.6M
鈭?/div>
40M
ETM3
1
1
1
1
1
1
1
ETM2
0
0
0
1
1
1
1
ETM1
0
1
1
0
0
1
1
EMT0
1
0
1
0
1
0
1
BUSY: CPU returns busy status. CPU will set this bit after write NVM bytes and clear it after
finished writing action. User can not read or write NVMDAT register while this bit is H
state. This bit is read only.
NVM Data Buffer
Bit:
7
D7
Mnemonic: NVMDAT
6
D6
5
D5
4
D4
3
D3
2
D2
Address: CFh
1
D1
0
D0
NVMDAT[7:0]: Each NVM byte is read/write content via this register. CPU will decode DCID5:0 bits
to address specific NVM byte. User must set EWR bit before write to these NVM
bytes. If user set lock bit of security register by external programmer, 64 bytes NVM
will be protected.
Program Status Word
Bit:
7
CY
Mnemonic: PSW
6
AC
5
F0
4
RS1
3
RS0
2
OV
Address: D0h
1
F1
0
P
CY: Carry flag: Set for an arithmetic operation which results in a carry being generated from the
ALU. It is also used as the accumulator for the bit operations.
AC: Auxiliary carry: Set when the previous operation resulted in a carry from the high order nibble.
F0: User flag 0: General purpose flag that can be set or cleared by the user.
RS.1
鈭?/div>
0: Register bank select bits:
RS1
0
0
1
1
RS0
0
1
0
1
Register bank
0
1
2
3
Address
00-07h
08-0Fh
10-17h
18-1Fh
- 31 -
Publication Release Date: August 16, 2002
Revision A1

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