Preliminary W77E516
Table 3. Instruction Timing for W77E516, continued
HEX
Op-Code
B4
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
E4
F4
C3
C2
B3
B2
14
18
19
1A
1B
1C
1D
1E
1F
16
17
15
A5
84
D4
D8
D9
DD
DA
DB
Instruction
Bytes
W77E516
Machine
Cycles
4
4
4
4
4
4
4
4
4
4
4
1
1
1
2
1
2
1
1
1
1
1
1
1
1
1
1
1
2
2
5
1
3
3
3
3
3
W77E516
Clock
Cycles
16
16
16
16
16
16
16
16
16
16
16
4
4
4
8
4
8
4
4
4
4
4
4
4
4
4
4
4
8
8
20
4
12
12
12
12
12
8032
Clock
Cycles
24
24
24
24
24
24
24
24
24
24
24
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
-
48
12
24
24
24
24
24
W77E516
vs.
8032 Speed
Ratio
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
3
3
3
1.5
3
1.5
3
3
3
3
3
3
3
3
3
3
3
1.5
-
2.4
3
2
2
2
2
2
CJNE A, #data, rel
CJNE @R0, #data, rel
CJNE @R1, #data, rel
CJNE R0, #data, rel
CJNE R1, #data, rel
CJNE R2, #data, rel
CJNE R3, #data, rel
CJNE R4, #data, rel
CJNE R5, #data, rel
CJNE R6, #data, rel
CJNE R7, #data, rel
CLR A
CPL A
CLR C
CLR bit
CPL C
CPL bit
DEC A
DEC R0
DEC R1
DEC R2
DEC R3
DEC R4
DEC R5
DEC R6
DEC R7
DEC @R0
DEC @R1
DEC direct
DEC DPTR
DIV AB
DA A
DJNZ R0, rel
DJNZ R1, rel
DJNZ R5, rel
DJNZ R2, rel
DJNZ R3, rel
3
3
3
3
3
3
3
3
3
3
3
1
1
1
2
1
2
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
2
2
2
2
2
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