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W77E516 Datasheet

  • W77E516

  • uC-Based Consumer IC > Controller IC > 8-Bit Microcontrolle...

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Preliminary W77E516
All the bits that generate interrupts can be set or reset by hardware, and thereby software initiated
interrupts can be generated. Each of the individual interrupts can be enabled or disabled by setting
or clearing a bit in the IE SFR. IE also has a global enable/disable bit EA, which can be cleared to
disable all the interrupts, except PFI, at once.
Priority Level Structure
There are two priority levels for the interrupts, high and low. The interrupt source can be individually
set to either high or low levels. Naturally, a higher priority interrupt cannot be interrupted by a lower
priority interrupt. However there exists a pre-defined hierarchy amongst the interrupts themselves.
This hierarchy comes into play when the interrupt controller has to resolve simultaneous requests
having the same priority level. This hierarchy is defined as shown below; the interrupts are
numbered starting from the highest priority to the lowest.
Table 7. Priority structure of interrupts
SOURCE
External Interrupt 0
Timer 0 Overflow
External Interrupt 1
Timer 1 Overflow
Serial Port
Timer 2 Overflow
Serial Port 1
External Interrupt 2
External Interrupt 3
External Interrupt 4
External Interrupt 5
Watchdog Timer
IE0
TF0
IE1
TF1
RI + TI
TF2 + EXF2
RI_1 + TI_1
IE2
IE3
IE4
IE5
WDIF
FLAG
2
3
4
5
6
7
8
9
10
11
12 (lowest)
PRIORITY LEVEL
1 (highest)
The interrupt flags are sampled every machine cycle. In the same machine cycle, the sampled
interrupts are polled and their priority is resolved. If certain conditions are met then the hardware will
execute an internally generated LCALL instruction which will vector the process to the appropriate
interrupt vector address. The conditions for generating the LCALL are
1. An interrupt of equal or higher priority is not currently being serviced.
2. The current polling cycle is the last machine cycle of the instruction currently being executed.
3. The current instruction does not involve a write to IP, IE, EIP or EIE registers and is not a RETI.
If any of these conditions are not met, then the LCALL will not be generated. The polling cycle is
repeated every machine cycle, with the interrupts sampled in the same machine cycle. If an
interrupt flag is active in one cycle but not responded to, and is not active when the above
conditions are met, the denied interrupt will not be serviced. This means that active interrupts are
not remembered; every polling cycle is new.
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