Preliminary W77E516
be set, which will also generate an interrupt. Setting the T2CR bit (T2MOD.3), the W77E516 allows
hardware to reset timer 2 automatically after the value of TL2 and TH2 have been captured.
Clock Source
Mode
input
div. by 4
osc/1
div. by 64
osc/16
div. by 1024 osc/256
1/4
T2M = CKCON.5
1
C/T2 = T2CON.1
0
T2CON.7
TL2
TH2
TF2
0
1
1/12
T2 = P1.0
TR2 = T2CON.2
T2EX = P1.1
Timer 2
Interrupt
RCAP2L RCAP2H
L
H
EXEN2 = T2CON.3
EXF2
T2CON.6
Figure 14. 16-Bit Capture Mode
Auto-reload Mode, Counting Up
The auto-reload mode as an up counter is enabled by clearing the CP/ RL2 bit in the T2CON
register and clearing the DCEN bit in T2MOD register. In this mode, Timer/Counter 2 is a 16 bit up
counter. When the counter rolls over from FFFFh, a reload is generated that causes the contents of
the RCAP2L and RCAP2H registers to be reloaded into the TL2 and TH2 registers. The reload
action also sets the TF2 bit. If the EXEN2 bit is set, then a negative transition of T2EX pin will also
cause a reload. This action also sets the EXF2 bit in T2CON.
Clock Source
Mode
input
div. by 4
osc/1
div. by 64
osc/16
div. by 1024 osc/256
T2M = CKCON.5
1/4
1/12
1
0
C/T2 = T2CON.1
0
T2CON.7
TL2
TH2
1
T2 = P1.0
TR2 = T2CON.2
T2EX = P1.1
TF2
Timer 2
Interrupt
RCAP2L RCAP2H
L
EXEN2 = T2CON.3
EXF2
T2CON.6
Figure 15. 16-Bit Auto-reload Mode, Counting Up
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