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PIC16F818/819

TABLE 2-1:

Address

Bank 1

80h

(1)

81h

82h

(1)

83h

(1)

84h

(1)

85h

86h

87h

88h

89h

8Ah

(1,2)

(1)

SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Details on

page:

Name

INDF

OPTION

PCL

STATUS

FSR

TRISA

TRISB

鈥?/div>

PCLATH

INTCON

PIE1

PIE2

PCON

OSCCON

OSCTUNE

鈥?/div>

PR2

SSPADD

SSPSTAT

鈥?/div>

ADRESL

ADCON1

Addressing this location uses contents of FSR to address data memory (not a physical register)

RBPU

INTEDG

T0CS

T0SE

PSA

PS2

PS1

PS0

0000 0000

1111 1111

0000 0000

23

17

23

16

23

39

43

鈥?/div>

23

18

19

21

22

38

36

鈥?/div>

68

71, 76

71

鈥?/div>

81

Program Counter's (PC) Least Significant Byte

IRP

RP1

RP0

TRISA5

(3)

TO

PD

Z

DC

C

0001 1xxx

xxxx xxxx

1111 1111

鈥?/div>

Indirect Data Memory Address Pointer

TRISA7

TRISA6

PORTA Data Direction Register (TRISA<4:0>

PORTB Data Direction Register

Unimplemented

鈥?/div>

GIE

鈥?/div>

PEIE

ADIE

鈥?/div>

IRCF2

鈥?/div>

TMR0IE

鈥?/div>

IRCF1

TUN5

Write Buffer for the upper 5 bits of the PC

INTE

鈥?/div>

EEIE

鈥?/div>

IRCF0

TUN4

RBIE

SSPIE

鈥?/div>

TUN3

TMR0IF

CCP1IE

鈥?/div>

IOFS

TUN2

INTF

TMR2IE

鈥?/div>

POR

鈥?/div>

TUN1

RBIF

TMR1IE

鈥?/div>

BOR

鈥?/div>

TUN0

---0 0000

0000 000x

-0-- 0000

---0 ----

---- --qq

-000 -0--

--00 0000

鈥?/div>

1111 1111

8Bh

8Ch

8Dh

8Eh

8Fh

90h

(1)

91h

92h

93h

94h

95h

96h

97h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Eh

9Fh

Legend:

Note 1:

2:

3:

Unimplemented

Timer2 Period Register

Synchronous Serial Port

SMP

CKE

(I

2

C mode) Address Register

P

S

R/W

UA

BF

0000 0000

鈥?/div>

xxxx xxxx

D/A

Unimplemented

A/D Result Register Lower Byte

ADFM

ADCS2

鈥?/div>

PCFG3

PCFG2

PCFG1

PCFG0

00-- 0000

x

= unknown,

u

= unchanged,

q

= value depends on condition, - = unimplemented, read as 鈥?鈥?

r

= reserved.

Shaded locations are unimplemented, read as 鈥?鈥?

These registers can be addressed from any bank.

The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are

transferred to the upper byte of the program counter.

Pin 5 is an input only; the state of the TRISA5 bit has no effect and will always read 鈥?鈥?

DS39598D-page 14

Preliminary

铮?/div>

2003 Microchip Technology Inc.

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