PIC16F818/819
2.2.2.3
INTCON Register
Note:
Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User
software should ensure the appropriate
interrupt flag bits are clear prior to
enabling an interrupt.
The INTCON register is a readable and writable regis-
ter that contains various enable and flag bits for the
TMR0 register overflow, RB port change and external
RB0/INT pin interrupts.
REGISTER 2-3:
INTCON: INTERRUPT CONTROL REGISTER (ADDRESS 0Bh, 8Bh, 10Bh, 18Bh)
R/W-0
GIE
bit 7
R/W-0
PEIE
R/W-0
TMR0IE
R/W-0
INTE
R/W-0
RBIE
R/W-0
TMR0IF
R/W-0
INTF
R/W-x
RBIF
bit 0
bit 7
GIE:
Global Interrupt Enable bit
1
= Enables all unmasked interrupts
0
= Disables all interrupts
PEIE:
Peripheral Interrupt Enable bit
1
= Enables all unmasked peripheral interrupts
0
= Disables all peripheral interrupts
TMR0IE:
TMR0 Overflow Interrupt Enable bit
1
= Enables the TMR0 interrupt
0
= Disables the TMR0 interrupt
INTE:
RB0/INT External Interrupt Enable bit
1
= Enables the RB0/INT external interrupt
0
= Disables the RB0/INT external interrupt
RBIE:
RB Port Change Interrupt Enable bit
1
= Enables the RB port change interrupt
0
= Disables the RB port change interrupt
TMR0IF:
TMR0 Overflow Interrupt Flag bit
1
= TMR0 register has overflowed (must be cleared in software)
0
= TMR0 register did not overflow
INTF:
RB0/INT External Interrupt Flag bit
1
= The RB0/INT external interrupt occurred (must be cleared in software)
0
= The RB0/INT external interrupt did not occur
RBIF:
RB Port Change Interrupt Flag bit
A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch
condition and allow flag bit RBIF to be cleared.
1
= At least one of the RB7:RB4 pins changed state (must be cleared in software)
0
= None of the RB7:RB4 pins have changed state
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
鈥?鈥?= Bit is set
U = Unimplemented bit, read as 鈥?鈥?/div>
鈥?鈥?= Bit is cleared
x = Bit is unknown
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DS39598D-page 18
Preliminary
铮?/div>
2003 Microchip Technology Inc.
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