PIC16F819 Datasheet

  • PIC16F819

  • 18/20-Pin Enhanced Flash Microcontrollers with nanoWatt Tech...

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  • 176页

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PIC16F818/819
3.3
Reading Data EEPROM Memory
The steps to write to EEPROM data memory are:
1.
If step 10 is not implemented, check the WR bit
to see if a write is in progress.
2. Write the address to EEADR. Make sure that the
address is not larger than the memory size of
the device.
3. Write the 8-bit data value to be programmed in
the EEDATA register.
4. Clear the EEPGD bit to point to EEPROM data
memory.
5. Set the WREN bit to enable program operations.
6. Disable interrupts (if enabled).
7. Execute the special five instruction sequence:
鈥?Write 55h to EECON2 in two steps (first to W,
then to EECON2)
鈥?Write AAh to EECON2 in two steps (first to W,
then to EECON2)
鈥?Set the WR bit
8. Enable interrupts (if using interrupts).
9. Clear the WREN bit to disable program
operations.
10. At the completion of the write cycle, the WR bit
is cleared and the EEIF interrupt flag bit is set
(EEIF must be cleared by firmware). If step 1 is
not implemented, then firmware should check
for EEIF to be set, or WR to clear, to indicate the
end of the program cycle.
To read a data memory location, the user must write the
address to the EEADR register, clear the EEPGD con-
trol bit (EECON1<7>) and then set control bit, RD
(EECON1<0>). The data is available in the very next
cycle in the EEDATA register; therefore, it can be read
in the next instruction (see Example 3-1). EEDATA will
hold this value until another read or until it is written to
by the user (during a write operation).
The steps to reading the EEPROM data memory are:
1.
Write the address to EEADR. Make sure that the
address is not larger than the memory size of
the device.
Clear the EEPGD bit to point to EEPROM data
memory.
Set the RD bit to start the read operation.
Read the data from the EEDATA register.
2.
3.
4.
EXAMPLE 3-1:
BANKSEL EEADR
MOVF
ADDR, W
MOVWF
EEADR
DATA EEPROM READ
Select Bank of EEADR
Data Memory Address
to read
Select Bank of EECON1
Point to Data memory
EE Read
Select Bank of EEDATA
W = EEDATA
;
;
;
;
BANKSEL EECON1
;
BCF
EECON1, EEPGD ;
BSF
EECON1, RD
;
BANKSEL EEDATA
;
MOVF
EEDATA, W
;
3.4
Writing to Data EEPROM Memory
EXAMPLE 3-2:
BANKSEL EECON1
DATA EEPROM WRITE
Select Bank of
EECON1
Wait for write
to complete
Select Bank of
EEADR
Data Memory
Address to write
Data Memory Value
to write
Select Bank of
EECON1
Point to DATA
memory
Enable writes
Disable INTs.
Write 55h
Write AAh
Set WR bit to
begin write
Enable INTs.
Disable writes
To write an EEPROM data location, the user must first
write the address to the EEADR register and the data
to the EEDATA register. Then, the user must follow a
specific write sequence to initiate the write for each
byte.
The write will not initiate if the write sequence is not
exactly followed (write 55h to EECON2, write AAh to
EECON2, then set WR bit) for each byte. We strongly
recommend that interrupts be disabled during this
code segment (see Example 3-2).
Additionally, the WREN bit in EECON1 must be set to
enable write. This mechanism prevents accidental
writes to data EEPROM due to errant (unexpected)
code execution (i.e., lost programs). The user should
keep the WREN bit clear at all times except when
updating EEPROM. The WREN bit is not cleared
by hardware
After a write sequence has been initiated, clearing the
WREN bit will not affect this write cycle. The WR bit will
be inhibited from being set unless the WREN bit is set.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EE Write Complete
Interrupt Flag bit (EEIF) is set. The user can either
enable this interrupt or poll this bit. EEIF must be
cleared by software.
;
;
BTFSC
EECON1, WR
;
GOTO
$-1
;
BANKSEL EEADR
;
;
MOVF
ADDR, W
;
MOVWF
EEADR
;
;
MOVF
VALUE, W
;
MOVWF
EEDATA
;
;
BANKSEL EECON1
;
;
BCF
EECON1, EEPGD ;
;
BSF
EECON1, WREN ;
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
BCF
INTCON, GIE
55h
EECON2
AAh
EECON2
EECON1, WR
INTCON, GIE
EECON1, WREN
;
;
;
;
;
;
;
;
;
铮?/div>
2003 Microchip Technology Inc.
Preliminary
Required
Sequence
DS39598D-page 27

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