(EECON1<0>). Once the read control bit is set, the
instruction cycle to read the data. This causes the
EECON1, RD鈥?/div>
instruction to be ignored. The data
is available in the very next cycle in the EEDATA and
EEDATH registers; therefore, it can be read as two
bytes in the following instructions. EEDATA and
EEDATH registers will hold this value until another read
or until it is written to by the user (during a write
operation).
The minimum erase block is 32 words. Only through
the use of an external programmer, or through ICSP
control, can larger blocks of program memory be bulk
erased. Word erase in the Flash array is not supported.
When initiating an erase sequence from the micro-
controller itself, a block of 32 words of program memory
is erased. The Most Significant 11 bits of the
EEADRH:EEADR point to the block being erased.
EEADR< 4:0> are ignored.
The EECON1 register commands the erase operation.
The EEPGD bit must be set to point to the Flash pro-
gram memory. The WREN bit must be set to enable
write operations. The FREE bit is set to select an erase
operation.
For protection, the write initiate sequence for EECON2
must be used.
After the 鈥淏SF
EECON1, WR鈥?/div>
instruction, the processor
requires two cycles to set up the erase operation. The
user must place two
NOP
instructions after the WR bit is
set. The processor will halt internal operations for the
typical 2 ms, only during the cycle in which the erase
takes place. This is not Sleep mode, as the clocks and
peripherals will continue to run. After the erase cycle,
the processor will resume operation with the third
instruction after the EECON1 write instruction.
EXAMPLE 3-3:
BANKSEL EEADRH
MOVF
ADDRH, W
MOVWF
EEADRH
FLASH PROGRAM READ
Select Bank of EEADRH
MS Byte of Program
Address to read
LS Byte of Program
Address to read
Select Bank of EECON1
Point to PROGRAM
memory
EE Read
Any instructions
here are ignored as
program memory is
read in second cycle
after BSF EECON1,RD
Select Bank of EEDATA
DATAL = EEDATA
DATAH = EEDATH
;
;
;
;
MOVF
ADDRL, W
;
MOVWF
EEADR
;
;
BANKSEL EECON1
;
BSF
EECON1, EEPGD ;
;
BSF
EECON1, RD
;
;
NOP
;
;
NOP
;
;
;
BANKSEL EEDATA
;
MOVF
EEDATA, W
;
MOVWF
DATAL
;
MOVF
EEDATH, W
;
MOVWF
DATAH
;
3.6.1
FLASH PROGRAM MEMORY
ERASE SEQUENCE
The sequence of events for erasing a block of internal
program memory location is:
1.
2.
Load EEADRH:EEADR with address of row
being erased.
Set EEPGD bit to point to program memory; set
WREN bit to enable writes and set FREE bit to
enable the erase.
Disable interrupts.
Write 55h to EECON2.
Write AAh to EECON2.
Set the WR bit. This will begin the row erase
cycle.
The CPU will stall for duration of the erase.
3.
4.
5.
6.
7.
DS39598D-page 28
Preliminary
铮?/div>
2003 Microchip Technology Inc.
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