PIC16F818/819
FIGURE 5-1:
BLOCK DIAGRAM OF
RA0/AN0:RA1/AN1 PINS
FIGURE 5-3:
Data
Bus
D
CK
D
WR
TRISA
CK
Q
Q
Q
N
Q
Analog
Input Mode
V
SS
V
SS
I/O pin
V
DD
V
DD
P
WR
PORTA
BLOCK DIAGRAM OF
RA2/AN2/V
REF
- PIN
Q
V
DD
V
DD
P
Data
Bus
WR
PORTA
D
CK
Q
Data Latch
D
Q
Data Latch
WR
TRISA
N
CK
Q
Analog
Input Mode
TTL
Input Buffer
TRIS Latch
V
SS
V
SS
I/O pin
TRIS Latch
RD TRISA
Q
TTL
Input Buffer
D
RD TRISA
Q
D
EN
EN
RD PORTA
RD PORTA
To A/D Module V
REF
- Input
To A/D Module Channel Input
To A/D Module Channel Input
FIGURE 5-2:
Data
Bus
WR
PORTA
BLOCK DIAGRAM OF
RA3/AN3/V
REF
+ PIN
Q
FIGURE 5-4:
Data
Bus
BLOCK DIAGRAM OF
RA4/AN4/T0CKI PIN
Q
D
CK
D
D
CK
D
Q
Q
V
DD
V
DD
P
WR
PORTA
Q
Q
V
DD
V
DD
P
Data Latch
I/O pin
V
SS
Data Latch
I/O pin
WR
TRISA
N
CK
Q
Analog
Input Mode
TTL
Input Buffer
RD TRISA
Q
EN
D
TRIS Latch
WR
TRISA
N
CK
Q
Analog
Input Mode
Schmitt Trigger
Input Buffer
TRIS Latch
V
SS
V
SS
V
SS
RD TRISA
Q
EN
RD PORTA
D
RD PORTA
To A/D Module V
REF
+ Input
To A/D Module Channel Input
TMR0 Clock Input
To A/D Module Channel Input
DS39598D-page 40
Preliminary
铮?/div>
2003 Microchip Technology Inc.
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