PIC16F818/819
FIGURE 5-5:
BLOCK DIAGRAM OF RA5/MCLR/V
PP
PIN
MCLRE
MCLR Circuit
MCLR Filter
Schmitt Trigger
Buffer
Data
Bus
RD TRIS V
SS
Q
EN
RD Port
MCLRE
D
Schmitt Trigger
Input Buffer
V
SS
RA5/MCLR/V
PP
FIGURE 5-6:
BLOCK DIAGRAM OF RA6/OSC2/CLKO PIN
From OSC1 Oscillator
Circuit
V
DD
P
RA6/OSC2/CLKO
(F
OSC
=
1x1)
N
V
SS
V
DD
CLKO (F
OSC
/4)
Data
Bus
WR
PORTA
D
CK
Q
Q
V
SS
V
DD
P
Data Latch
D
WR
TRISA
CK
Q
N
Q
(F
OSC
=
1x0,011)
V
SS
TRIS Latch
RD TRISA
Q
EN
RD PORTA
D
Schmitt Trigger
Input Buffer
(F
OSC
=
1x0,011)
Note 1:
I/O pins have protection diodes to V
DD
and V
SS
.
2:
CLKO signal is 1/4 of the F
OSC
frequency.
铮?/div>
2003 Microchip Technology Inc.
Preliminary
DS39598D-page 41
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