PIC16F818/819
TABLE 5-3:
Name
RB0/INT
RB1/SDI/SDA
RB2/SDO/CCP1
PORTB FUNCTIONS
Bit#
bit 0
bit 1
bit 2
Buffer
Function
TTL/ST
(1)
Input/output pin or external interrupt input.
Internal software programmable weak pull-up.
TTL/ST
(5)
Input/output pin, SPI data input pin or I
2
C data I/O pin.
Internal software programmable weak pull-up.
TTL/ST
(4)
Input/output pin, SPI data output pin or
Capture input/Compare output/PWM output pin.
Internal software programmable weak pull-up.
TTL/ST
(2)
Input/output pin, Capture input/Compare output/PWM output pin
or programming in LVP mode. Internal software programmable
weak pull-up.
TTL/ST
(5)
Input/output pin or SPI and I
2
C clock pin (with interrupt-on-change).
Internal software programmable weak pull-up.
TTL
Input/output pin or SPI slave select pin (with interrupt-on-change).
Internal software programmable weak pull-up.
RB3/CCP1/PGM
(3)
bit 3
RB4/SCK/SCL
RB5/SS
RB6/T1OSO/T1CKI/
PGC
RB7/T1OSI/PGD
bit 4
bit 5
bit 6
TTL/ST
(2)
Input/output pin, Timer1 oscillator output pin, Timer1 clock input pin or
serial programming clock (with interrupt-on-change).
Internal software programmable weak pull-up.
TTL/ST
(2)
Input/output pin, Timer1 oscillator input pin or serial programming data
(with interrupt-on-change).
Internal software programmable weak pull-up.
bit 7
Legend:
TTL = TTL input, ST = Schmitt Trigger input
Note 1:
This buffer is a Schmitt Trigger input when configured as the external interrupt.
2:
This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3:
Low-Voltage ICSP Programming (LVP) is enabled by default which disables the RB3 I/O function. LVP
must be disabled to enable RB3 as an I/O pin and allow maximum compatibility to the other 18-pin
mid-range devices.
4:
This buffer is a Schmitt Trigger input when configured for CCP or SSP mode.
5:
This buffer is a Schmitt Trigger input when configured for SPI or I
2
C mode.
TABLE 5-4:
Address
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Name
Bit 7
RB7
RBPU
Bit 6
RB6
INTEDG
Bit 5
RB5
T0CS
Bit 4
RB4
T0SE
Bit 3
RB3
PSA
Bit 2
RB2
PS2
Bit 1
RB1
PS1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
06h, 106h PORTB
86h, 186h TRISB
81h, 181h Option
RB0
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
PS0
1111 1111 1111 1111
PORTB Data Direction Register
Legend:
x
= unknown,
u
= unchanged. Shaded cells are not used by PORTB.
DS39598D-page 44
Preliminary
铮?/div>
2003 Microchip Technology Inc.
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