PIC16F819 Datasheet

IC型号：
PIC16F819
PDF描述：
18/20-Pin Enhanced Flash Microcontrollers with nanoWatt Tech...
文件大小：
68.31KB
PDF页数：
176页
芯片厂家：
MICROCHIP

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PIC16F818/819

9.3

PWM Mode

9.3.1

PWM PERIOD

In Pulse Width Modulation (PWM) mode, the CCP1 pin

produces up to a 10-bit resolution PWM output. Since

the CCP1 pin is multiplexed with the PORTB data latch,

the TRISB<x> bit must be cleared to make the CCP1

pin an output.

Note:

Clearing the CCP1CON register will force

the CCP1 PWM output latch to the default

low level. This is not the PORTB I/O data

latch.

The PWM period is specified by writing to the PR2

following formula.

EQUATION 9-1:

PWM Period = [(PR2) + 1] 鈥?4 鈥?T

OSC

鈥?/div>

(TMR2 Prescale Value)

PWM frequency is defined as 1/[PWM period].

When TMR2 is equal to PR2, the following three events

occur on the next increment cycle:

鈥?TMR2 is cleared

鈥?The CCP1 pin is set (exception: if PWM duty

cycle = 0%, the CCP1 pin will not be set)

鈥?The PWM duty cycle is latched from CCPR1L into

CCPR1H

Note:

The Timer2 postscaler (see

Section 8.0

鈥淭imer2 Module鈥?

is not used in the

determination of the PWM frequency. The

postscaler could be used to have a servo

update rate at a different frequency than

the PWM output.

Figure 9-3 shows a simplified block diagram of the

CCP module in PWM mode.

For a step by step procedure on how to set up the CCP

module for PWM operation, see

Section 9.3.3 鈥淪etup

for PWM Operation鈥?

FIGURE 9-3:

SIMPLIFIED PWM BLOCK

DIAGRAM

CCP1CON<5:4>

Duty Cycle Registers

CCPR1L

CCPR1H (Slave)

9.3.2

Comparator

CCP1 pin

TMR2

(Note 1)

TRISB<x>

Clear Timer,

CCP1 pin and

latch D.C.

PWM DUTY CYCLE

Comparator

The PWM duty cycle is specified by writing to the

CCPR1L register and to the CCP1CON<5:4> bits. Up

to 10-bit resolution is available. The CCPR1L contains

the eight MSbs and the CCP1CON<5:4> contains the

two LSbs. This 10-bit value is represented by

CCPR1L:CCP1CON<5:4>. The following equation is

used to calculate the PWM duty cycle in time.

PR2

EQUATION 9-2:

Note 1:

8-bit timer is concatenated with 2-bit internal Q clock

or 2 bits of the prescaler to create 10-bit time base.

PWM Duty Cycle = (CCPR1L:CCP1CON<5:4>) 鈥?/div>

OSC

鈥?(TMR2 Prescale Value)

CCPR1L and CCP1CON<5:4> can be written to at any

time but the duty cycle value is not latched into

CCPR1H until after a match between PR2 and TMR2

occurs (i.e., the period is complete). In PWM mode,

CCPR1H is a read-only register.

The CCPR1H register and a 2-bit internal latch are

used to double-buffer the PWM duty cycle. This

double-buffering is essential for glitchless PWM

operation.

When the CCPR1H and 2-bit latch match TMR2,

concatenated with an internal 2-bit Q clock or 2 bits of

the TMR2 prescaler, the CCP1 pin is cleared.

A PWM output (Figure 9-4) has a time base (period)

and a time that the output stays high (duty cycle). The

frequency of the PWM is the inverse of the period

(1/period).

FIGURE 9-4:

Period

PWM OUTPUT

Duty Cycle

TMR2 = PR2

TMR2 = Duty Cycle

TMR2 = PR2

DS39598D-page 68

Preliminary

铮?/div>

2003 Microchip Technology Inc.

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