PIC16F818/819
REGISTER 10-1:
SSPSTAT: SYNCHRONOUS SERIAL PORT STATUS REGISTER (ADDRESS 94h)
R/W-0
SMP
bit 7
bit 7
SMP:
SPI Data Input Sample Phase bit
SPI Master mode:
1
= Input data sampled at end of data output time
0
= Input data sampled at middle of data output time (Microwire)
SPI Slave mode:
This bit must be cleared when SPI is used in Slave mode.
I
2
C mode:
This bit must be maintained clear.
CKE:
SPI Clock Edge Select bit
SPI mode, CKP =
0
:
1
= Data transmitted on rising edge of SCK (Microwire alternate)
0
= Data transmitted on falling edge of SCK
SPI mode, CKP =
1:
1
= Data transmitted on falling edge of SCK (Microwire alternate)
0
= Data transmitted on rising edge of SCK
I
2
C mode:
This bit must be maintained clear.
D/A:
Data/Address bit (I
2
C mode only)
In I
2
C Slave mode:
1
= Indicates that the last byte received was data
0
= Indicates that the last byte received was address
P:
Stop bit
(1)
(I
2
C mode only)
1
= Indicates that a Stop bit has been detected last
0
= Stop bit was not detected last
S:
Start bit
(1)
(I
2
C mode only)
1
= Indicates that a Start bit has been detected last (this bit is 鈥?鈥?on Reset)
0
= Start bit was not detected last
R/W:
Read/Write Information bit (I
2
C mode only)
Holds the R/W bit information following the last address match and is only valid from address
match to the next Start bit, Stop bit or ACK bit.
1
= Read
0
= Write
UA:
Update Address bit (10-bit I
2
C mode only)
1
= Indicates that the user needs to update the address in the SSPADD register
0
= Address does not need to be updated
BF:
Buffer Full Status bit
Receive (SPI and I
2
C modes):
1
= Receive complete, SSPBUF is full
0
= Receive not complete, SSPBUF is empty
Transmit (In I
2
C mode only):
1
= Transmit in progress, SSPBUF is full (8 bits)
0
= Transmit complete, SSPBUF is empty
Note 1:
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
鈥?鈥?= Bit is set
U = Unimplemented bit, read as 鈥?鈥?/div>
鈥?鈥?= Bit is cleared
x = Bit is unknown
This bit is cleared when the SSP module is disabled (i.e., the SSPEN bit is cleared).
R/W-0
CKE
R-0
D/A
R-0
P
R-0
S
R-0
R/W
R-0
UA
R-0
BF
bit 0
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DS39598D-page 72
Preliminary
铮?/div>
2003 Microchip Technology Inc.
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