= Left justified, 6 Least Significant bits of ADRESL are read as 鈥?鈥?/div>
ADCS2:
A/D Clock Divide by 2 Select bit
1
= A/D Clock source is divided by 2 when system clock is used
0
= Disabled
Unimplemented:
Read as 鈥?鈥?/div>
PCFG<3:0>:
A/D Port Configuration Control bits
PCFG
0000
0001
0010
0011
0100
0101
011x
1000
1001
1010
1011
1100
1101
1110
1111
AN4
A
A
A
A
D
D
D
A
A
A
A
A
D
D
D
AN3
A
V
REF+
A
V
REF+
A
V
REF+
D
V
REF+
A
V
REF+
V
REF+
V
REF+
V
REF+
D
V
REF+
AN2
A
A
A
A
D
D
D
V
REF-
A
A
V
REF-
V
REF-
V
REF-
D
V
REF-
AN1
A
A
A
A
A
A
D
A
A
A
A
A
A
D
D
AN0
A
A
A
A
A
A
D
A
A
A
A
A
A
A
A
V
REF
+
AV
DD
AN3
AV
DD
AN3
AV
DD
AN3
AV
DD
AN3
AV
DD
AN3
AN3
AN3
AN3
AV
DD
AN3
V
REF
-
AV
SS
AV
SS
AV
SS
AV
SS
AV
SS
AV
SS
AV
SS
AN2
AV
SS
AV
SS
AN2
AN2
AN2
AV
SS
AN2
C/R
5/0
4/1
5/0
4/1
3/0
2/1
0/0
3/2
5/0
4/1
3/2
3/2
2/2
1/0
1/2
R/W-0
ADCS2
U-0
鈥?/div>
U-0
鈥?/div>
R/W-0
PCFG3
R/W-0
PCFG2
R/W-0
PCFG1
R/W-0
PCFG0
bit 0
bit 6
bit 5-4
bit 3-0
A = Analog input
D = Digital I/O
C/R = Number of analog input channels/Number of A/D voltage references
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
鈥?鈥?= Bit is set
U = Unimplemented bit, read as 鈥?鈥?/div>
鈥?鈥?= Bit is cleared
x = Bit is unknown
DS39598D-page 82
Preliminary
铮?/div>
2003 Microchip Technology Inc.
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