PIC16F818/819
The ADRESH:ADRESL registers contain the result of
the A/D conversion. When the A/D conversion is
complete, the result is loaded into the A/D Result register
pair, the GO/DONE bit (ADCON0<2>) is cleared and
A/D Interrupt Flag bit, ADIF, is set. The block diagram of
the A/D module is shown in Figure 11-1.
After the A/D module has been configured as desired,
the selected channel must be acquired before the con-
version is started. The analog input channels must
have their corresponding TRIS bits selected as inputs.
To determine sample time, see
Section 11.1 鈥淎/D
Acquisition Requirements鈥?
After this sample time
has elapsed, the A/D conversion can be started.
3.
4.
5.
These steps should be followed for doing an A/D
conversion:
1.
Configure the A/D module:
鈥?Configure analog pins/voltage reference and
digital I/O (ADCON1)
鈥?Select A/D input channel (ADCON0)
鈥?Select A/D conversion clock (ADCON0)
鈥?Turn on A/D module (ADCON0)
Configure A/D interrupt (if desired):
鈥?Clear ADIF bit
鈥?Set ADIE bit
鈥?Set GIE bit
Wait the required acquisition time.
Start conversion:
鈥?Set GO/DONE bit (ADCON0)
Wait for A/D conversion to complete by either:
鈥?Polling for the GO/DONE bit to be cleared
(with interrupts disabled); OR
鈥?Waiting for the A/D interrupt
Read A/D Result register pair
(ADRESH:ADRESL), clear bit ADIF if required.
For next conversion, go to step 1 or step 2 as
required. The A/D conversion time per bit is
defined as T
AD
. A minimum wait of 2 T
AD
is
required before the next acquisition starts.
2.
6.
7.
FIGURE 11-1:
A/D BLOCK DIAGRAM
CHS<3:0>
100
RA4/AN4
011
RA3/AN3/V
REF
+
010
V
IN
(Input Voltage)
AV
DD
A/D
Converter
V
REF
+
(Reference
Voltage)
PCFG<3:0>
001
RA1/AN1
000
RA0/AN0
RA2/AN2/V
REF
-
V
REF
-
(Reference
Voltage)
AV
SS
PCFG<3:0>
铮?/div>
2003 Microchip Technology Inc.
Preliminary
DS39598D-page 83
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