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PIC16F819 Datasheet

  • PIC16F819

  • 18/20-Pin Enhanced Flash Microcontrollers with nanoWatt Tech...

  • 68.31KB

  • 176页

  • MICROCHIP   MICROCHIP

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PIC16F818/819
11.1
A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (C
HOLD
) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 11-2. The source
impedance (R
S
) and the internal sampling switch (R
SS
)
impedance directly affect the time required to charge
the capacitor C
HOLD
. The sampling switch (R
SS
)
impedance varies over the device voltage (V
DD
), see
Figure 11-2.
The maximum recommended imped-
ance for analog sources is 2.5 k鈩?
As the impedance
is decreased, the acquisition time may be decreased.
After the analog input channel is selected (changed),
this acquisition must be done before the conversion
can be started.
To calculate the minimum acquisition time,
Equation 11-1 may be used. This equation assumes
that 1/2 LSb error is used (1024 steps for the A/D). The
1/2 LSb error is the maximum error allowed for the A/D
to meet its specified resolution.
To calculate the minimum acquisition time, T
ACQ
, see
the PICmicro
庐
Mid-Range MCU Family Reference
Manual (DS33023).
EQUATION 11-1:
T
ACQ
ACQUISITION TIME
=
Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
=
=
=
=
=
=
=
T
AMP
+ T
C
+ T
COFF
2
碌s
+ T
C
+ [(Temperature -25掳C)(0.05
碌s/掳C)]
C
HOLD
(R
IC
+ R
SS
+ R
S
) In(1/2047)
-120 pF (1 k鈩?+ 7 k鈩?+ 10 k鈩? In(0.0004885)
16.47
碌s
2
碌s
+ 16.47
碌s
+ [(50掳C 鈥?25掳C)(0.05
碌s/掳C)
19.72
碌s
T
C
T
ACQ
Note 1:
The reference voltage (V
REF
) has no effect on the equation since it cancels itself out.
2:
The charge holding capacitor (C
HOLD
) is not discharged after each conversion.
3:
The maximum recommended impedance for analog sources is 10 k鈩? This is required to meet the pin
leakage specification.
4:
After a conversion has completed, a 2.0 T
AD
delay must complete before acquisition can begin again.
During this time, the holding capacitor is not connected to the selected A/D input channel.
FIGURE 11-2:
ANALOG INPUT MODEL
V
DD
V
T
= 0.6V
R
IC
鈮?/div>
1k
Sampling
Switch
SS
R
SS
C
HOLD
= DAC Capacitance
= 51.2 pF
V
SS
Legend:
C
PIN
= input capacitance
V
T
= threshold voltage
I
LEAKAGE
= leakage current at the pin due to
various junctions
R
IC
= interconnect resistance
SS
= sampling switch
C
HOLD
= sample/hold capacitance (from DAC)
Rs
ANx
VA
C
PIN
5 pF
V
T
= 0.6V
I
LEAKAGE
卤
500 nA
V
DD
6V
5V
4V
3V
2V
5 6 7 8 9 10 11
Sampling Switch
(k鈩?
DS39598D-page 84
Preliminary
铮?/div>
2003 Microchip Technology Inc.

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