PIC16F819 Datasheet

IC型号：
PIC16F819
PDF描述：
18/20-Pin Enhanced Flash Microcontrollers with nanoWatt Tech...
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68.31KB
PDF页数：
176页
芯片厂家：
MICROCHIP

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PIC16F818/819

11.5

A/D Operation During Sleep

11.6

Effects of a Reset

The A/D module can operate during Sleep mode. This

requires that the A/D clock source be set to RC

(ADCS1:ADCS0 =

11).

When the RC clock source is

selected, the A/D module waits one instruction cycle

before starting the conversion. This allows the

SLEEP

instruction to be executed which eliminates all digital

switching noise from the conversion. When the conver-

sion is completed, the GO/DONE bit will be cleared and

the result loaded into the ADRES register. If the A/D

interrupt is enabled, the device will wake-up from

Sleep. If the A/D interrupt is not enabled, the A/D

module will then be turned off, although the ADON bit

will remain set.

When the A/D clock source is another clock option (not

RC), a

SLEEP

instruction will cause the present conver-

sion to be aborted and the A/D module to be turned off,

though the ADON bit will remain set.

Turning off the A/D places the A/D module in its lowest

current consumption state.

Note:

For the A/D module to operate in Sleep,

the A/D clock source must be set to RC

(ADCS1:ADCS0 =

11).

To perform an A/D

conversion in Sleep, ensure the

SLEEP

instruction immediately follows the

instruction that sets the GO/DONE bit.

A device Reset forces all registers to their Reset state.

The A/D module is disabled and any conversion in

progress is aborted. All A/D input pins are configured

as analog inputs.

The value that is in the ADRESH:ADRESL registers

is not modified for a Power-on Reset. The

ADRESH:ADRESL registers will contain unknown data

after a Power-on Reset.

11.7

Use of the CCP Trigger

An A/D conversion can be started by the 鈥渟pecial event

trigger鈥?of the CCP module. This requires that the

CCP1M3:CCP1M0

bits

(CCP1CON<3:0>)

programmed as 鈥?011鈥?and that the A/D module is

enabled (ADON bit is set). When the trigger occurs, the

GO/DONE bit will be set, starting the A/D conversion

and the Timer1 counter will be reset to zero. Timer1 is

reset to automatically repeat the A/D acquisition period

with minimal software overhead (moving the

ADRESH:ADRESL to the desired location). The appro-

priate analog input channel must be selected and the

minimum acquisition done before the 鈥渟pecial event

trigger鈥?sets the GO/DONE bit (starts a conversion).

If the A/D module is not enabled (ADON is cleared),

then the 鈥渟pecial event trigger鈥?will be ignored by the

A/D module but will still reset the Timer1 counter.

TABLE 11-2:

Address

REGISTERS/BITS ASSOCIATED WITH A/D

Bit 7

GIE

鈥?/div>

Bit 6

PEIE

ADIF

ADIE

Bit 5

TMR0IE

鈥?/div>

Bit 4

INTE

鈥?/div>

Bit 3

RBIE

SSPIF

SSPIE

Bit 2

TMR0IF

CCP1IF

CCP1IE

Bit 1

INTF

Bit 0

RBIF

Value on

POR, BOR

0000 000x

Value on

all other

Resets

0000 000u

-0-- 0000

uuuu uuuu

0000 00-0

00-- 0000

uuu0 0000

1111 1111

Name

0Bh,8Bh

INTCON

10Bh,18Bh

0Ch

8Ch

1Eh

9Eh

1Fh

9Fh

05h

85h

Legend:

PIR1

PIE1

ADRESH

ADRESL

ADCON1

PORTA

TRISA

TMR2IF TMR1IF

-0-- 0000

TMR2IE TMR1IE

-0-- 0000

xxxx xxxx

A/D Result Register High Byte

A/D Result Register Low Byte

CHS2

鈥?/div>

RA5

CHS1

鈥?/div>

RA4

CHS0 GO/DONE

PCFG3

RA3

PCFG2

RA2

鈥?/div>

PCFG1

RA1

ADON

PCFG0

RA0

ADFM

RA7

ADCS2

RA6

ADCON0 ADCS1 ADCS0

0000 00-0

00-- 0000

xxx0 0000

1111 1111

TRISA7 TRISA6 TRISA5 PORTA Data Direction Register

= unknown,

= unchanged,

= unimplemented, read as 鈥?鈥? Shaded cells are not used for A/D conversion.

铮?/div>

2003 Microchip Technology Inc.

Preliminary

DS39598D-page 87

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