鈥?/div>
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during Sleep
WDT Reset during normal operation
WDT wake-up during Sleep
Brown-out Reset (BOR)
Some registers are not affected in any Reset condition.
Their status is unknown on POR and unchanged in any
other Reset. Most other registers are reset to a 鈥淩eset
state鈥?on Power-on Reset (POR), on the MCLR and
WDT Reset, on MCLR Reset during Sleep, and Brown-
out Reset (BOR). They are not affected by a WDT
wake-up which is viewed as the resumption of normal
operation. The TO and PD bits are set or cleared differ-
ently in different Reset situations as indicated in
Table 12-3. These bits are used in software to deter-
mine the nature of the Reset. Upon a POR, BOR or
wake-up from Sleep, the CPU requires approximately
5-10
碌s
to become ready for code execution. This
delay runs in parallel with any other timers. See
Table 12-4 for a full description of Reset states of all
registers.
A simplified block diagram of the on-chip Reset circuit
is shown in Figure 12-1.
FIGURE 12-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
Reset
MCLR
WDT
Module
V
DD
Rise
Detect
V
DD
Brown-out
Reset
BOREN
OST/PWRT
OST
10-bit Ripple Counter
OSC1
R
Q
Chip_Reset
Power-on Reset
S
WDT
Sleep
Time-out
Reset
PWRT
INTRC
31.25 kHz
10-bit Ripple Counter
Enable PWRT
Enable OST
铮?/div>
2003 Microchip Technology Inc.
Preliminary
DS39598D-page 91
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