PIC16F818/819
FIGURE 12-3:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO V
DD
THROUGH
PULL-UP RESISTOR)
V
DD
MCLR
Internal POR
T
PWRT
PWRT Time-out
T
OST
OST Time-out
Internal Reset
FIGURE 12-4:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO V
DD
THROUGH
RC NETWORK): CASE 1
V
DD
MCLR
Internal POR
T
PWRT
PWRT Time-out
T
OST
OST Time-out
Internal Reset
FIGURE 12-5:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO V
DD
THROUGH
RC NETWORK): CASE 2
V
DD
MCLR
Internal POR
T
PWRT
PWRT Time-out
T
OST
OST Time-out
Internal Reset
铮?/div>
2003 Microchip Technology Inc.
Preliminary
DS39598D-page 95
prev
next