patible signals). See the
tion for header connections.
5) Connect a 1.8V, 300mA power supply to VCC.
Connect the ground terminal of this supply to GND.
6) Connect a 3.3V, 150mA power supply to VCLK.
Connect the ground terminal of this supply to GND.
7) Connect a 3.3V, 350mA power supply to VPECL.
Connect the ground terminal of this supply to GND.
8) Turn on all of the power supplies.
9) Enable the signal generators. Set the clock signal
. Set the analog input signal genera-
鈮?/div>
2V
P-P
. The signal generators should be
phase-locked.
10) Enable the logic analyzer.
11) Collect data using the logic analyzer.
Power Supplies
The MAX1124 EV kit requires separate analog, clock,
and buffer power supplies for best performance. A 1.8V
power supply is used to power the analog and digital
portion of the MAX1124. The on-board clock circuitry is
powered by a 3.3V power supply. A separate 3.3V
power supply is used to power the output buffers
(U3鈥揢6) of the EV kit.
Evaluates: MAX1121鈥揗AX1124
Clock
The MAX1124 requires a differential clock input signal.
An on-board clock-shaping circuit generates a differen-
tial clock signal from an AC sine-wave signal applied to
the clock-input SMA connector (J2). The input signal
should not exceed an amplitude of 2.6V
P-P
. The fre-
quency of the signal should not exceed 250MHz for the
MAX1124. The frequency of the sinusoidal input signal
determines the sampling frequency (f
CLK
) of the ADC.
A differential line receiver (U2), processes the input sig-
nal to generate the required clock signal.
Clock Divider
The MAX1124 features an internal divide-by-two clock
divider. Use jumper JU4 to enable/disable this feature.
See
Table
1 for shunt positions.
Detailed Description
The MAX1124 EV kit is a fully assembled and tested cir-
cuit board that contains all the components necessary to
evaluate the performance of the MAX1121 (8-bit,
250Msps), MAX1122 (10-bit, 170Msps), MAX1123 (10-bit,
210Msps), and MAX1124 (10-bit, 250Msps) LVDS-out-
put ADCs. The EV kit comes with the MAX1124 installed,
which can be evaluated with a maximum clock frequen-
cy (f
CLK
) of 250MHz. The MAX1124 accepts differential
input signals; however, an on-board transformer (T2)
converts a readily available single-ended source output
to the required differential signal.
Output level translators (U3鈥揢6) buffer and convert the
LVDS output signals of the MAX1124 to higher-voltage
LVPECL signals, which can be captured by a wide vari-
ety of logic analyzers. The LVDS outputs are accessed
at headers J4 and J5. The LVPECL outputs are
accessed at headers J6 and J7.
The EV kit is designed as a four-layer PC board to opti-
mize the performance of the MAX1124. Separate ana-
log, clock, and buffer power planes minimize noise-
coupling between analog and digital signals. For ana-
log and clock inputs, 50鈩?coplanar transmission lines
are used. For all digital LVDS outputs, 100鈩?differential
coplanar transmission lines are used. All LVDS differen-
tial outputs are properly terminated with 100鈩?termina-
tion resistors between true and complementary digital
outputs. The trace lengths of the 100鈩?differential LVDS
lines are matched to within a few thousandths of an
inch to minimize layout-dependent delays.
Input Signal
The MAX1124 accepts differential analog input signals.
The MAX1124 EV kit only requires a single-ended ana-
log input signal with an amplitude
鈮?V
P-P
provided by
the user. An on-board transformer takes the single-
ended analog input and generates a differential analog
signal at the ADCs differential input pins.
Table
1. Clock Divider Shunt Settings (JU4)
SHUNT
POSITION
1-2*
2-3
MAX1124
CLKDIV PIN
VCC
GND
DESCRIPTION
Clock signal divided by 1
Clock signal divided by 2
*Default
Configuration: JU4 (1-2).
_______________________________________________________________________________________
3
1
2
3
4
5
6
7
8
9
10
