MAX1124 Evaluation Kit
Evaluates: MAX1121鈥揗AX1124
Optional Secondary Input Transformer
Using the optional on-board secondary transformer can
reduce common-mode signal levels and marginally
improve performance of the MAX1124. To use this
transformer, follow the directions below:
1) Cut the trace at R43.
2) Install 0鈩?resistors at R10 and R12.
3) Remove C14.
4) Connect the analog signal source to J1 instead of J3.
Output Bit Locations
The digital outputs of the ADC are connected to two 40-
pin headers (J4 and J5). PC board trace lengths are
matched to minimize output skew and improve perfor-
mance of the device. In addition, four drivers (U3鈥揢6)
buffer and level-translate the ADC鈥檚 digital outputs to
LVPECL-compatible signals. The drivers increase the
differential voltage swing, and are able to drive large
capacitive loads, which may be present at the logic
analyzer connection. The outputs of the buffers are
connected to two 40-pin headers (J6 and J7). See
Table
4 for header J4鈥揓7 bit locations.
Reference Voltage
There are two methods to set the full-scale range of the
MAX1124. The MAX1124 EV kit can be configured to
use the MAX1124鈥檚 internal reference, or a stable, low-
noise external reference can be applied to the REFIO
pad. Jumper JU5 controls which reference source is
used. See
Table
2 for shunt settings.
Table
4. Output Bit Locations
(MAX1122/MAX1123/MAX1124) (JU3)
BIT
D9
D8
D7
D6
D5
P
N
P
N
P
N
P
N
P
N
P
N
P
N
P
N
P
N
P
N
P
N
P
N
UNBUFFERED
(LVDS)
J6-10
J6-9
J6-16
J6-15
J6-22
J6-21
J6-28
J6-27
J6-34
J6-33
J6-40
J6-39
J7-8
J7-7
J7-14
J7-13
J7-20
J7-19
J7-26
J7-25
J6-4
J6-3
J7-2
J7-1
BUFFERED
(LVPECL)
J4-10
J4-9
J4-16
J4-15
J4-22
J4-21
J4-28
J4-27
J4-34
J4-33
J4-40
J4-39
J5-8
J5-7
J5-14
J5-13
J5-20
J5-19
J5-26
J5-25
J4-4
J4-3
J5-2
J5-1
LSB
Overrange bit
Clock output
signal
Data bits
DESCRIPTION
MSB
Table
2. Reference Shunt Settings (JU5)
SHUNT
POSITION
1-2
2-3*
DESCRIPTION
Internal reference disabled; apply a stable
reference voltage at the REFIO pad
Internal reference enabled
*Default
configuration: JU5 (2-3).
Output Signal
The MAX1124 features a single,10-bit, parallel, LVDS-
compatible, digital output bus. The digital outputs also
feature a clock bit (CLK) for data synchronization, and
a data overrange bit. See the
Output Bit Locations
sec-
tion for header connections.
Output Format
The digital output coding can be chosen to be either in
two鈥檚 complement or straight offset binary format by
configuring jumper JU3. See
Table
3 for shunt settings.
D4
D3
D2
D1
D0
Table
3. Output Format Shunt Settings
(JU3)
SHUNT
POSITION
1-2
2-3*
MAX1124
T/B
PIN
VCC
GND
DESCRIPTION
Digital output in straight offset
binary
Digital output in two's complement
OR
DCO
*Default
configuration: JU3 (2-3).
*Default
configuration: JU3 (2-3).
4
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