CD74HC40103, CD74HCT40103
Pinout
CD74HC40103, CD74HCT40103
(PDIP, SOIC)
TOP VIEW
CP 1
MR 2
TE 3
P0 4
P1 5
P2 6
P3 7
GND 8
16 V
CC
15 PE (SYNC)
14 TC
13 P7
12 P6
11 P5
10 P4
9 PL (ASYNC)
Functional Diagram
14
TC
13
12
11
10
7
6
5
4
GND
8
MR
V
CC
TE
CP
3
1
PE
15
PL
9
P7
P6
P5
P4
P3
P2
P1
P0
2
16
TRUTH TABLE
CONTROL INPUTS
MR
1
1
1
1
0
PL
1
1
1
0
X
PE
1
1
0
X
X
TE
1
0
X
X
X
Asynchronously
PRESET MODE
Synchronous
Inhibit Counter
Count Down
Preset On Next Positive Clock Transition
Preset Asychronously
Clear to Maximum Count
ACTION
NOTE:
1 = High Level.
0 = Low Level.
X = Don鈥檛 Care.
Clock connected to clock input.
Synchronous Operation: changes occur on negative-to-positive clock transitions.
Load Inputs: MSB = P7, LSB = P0.
2