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CD74HC40103 Datasheet

  • CD74HC40103

  • High Speed CMOS Logic 8-Stage Synchronous Down Counters

  • 156.00KB

  • 14页

  • TI

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CD74HC40103, CD74HCT40103
Switching Speci铿乧ations
Input t
r
, t
f
= 6ns
(Continued)
25
o
C
MIN
-
-
-
-
-
-
TYP
-
23
-
-
25
27
MAX
55
-
15
10
-
-
-40
o
C TO
85
o
C
MIN
-
-
-
-
-
-
MAX
69
-
19
10
-
-
-55
o
C TO
125
o
C
MIN
-
-
-
-
-
-
MAX
83
-
22
10
-
-
UNITS
ns
ns
ns
pF
MHz
pF
PARAMETER
MR to TC
TEST
SYMBOL CONDITIONS
t
PLH,
t
PHL
t
THL
, t
TLH
C
IN
f
MAX
C
PD
C
L
= 50pF
C
L
= 15pF
C
L
= 50pF
C
L
= 50pF
C
L
= 15pF
-
V
CC
(V)
4.5
5
4.5
-
5
5
Output Transition Time
Input Capacitance
CP Maximum Frequency
Power Dissipation Capacitance
(Notes 5, 6)
NOTES:
4. Noncascaded operation only. With cascaded counters clock-to-terminal count propagation delays, count enables (PE or TE)-to-clock SET
UP TIMES, and count enables (PE or TE)-to-clock HOLD TIMES determine maximum clock frequency. For example, with these HC de-
vices:
1
1
-
-
C
P
f
MAX
= ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- = ----------------------------
鈮?/div>
11MHz
60
+
30
+
0
CP-to-TC prop delay + TE-to-CP Setup Time + TE-to-CP Hold Time
5. C
PD
is used to determine the dynamic power consumption, per package.
6. P
D
= V
CC2
f
i
+ C
L
V
CC2
f
o
where f
i
= Input Frequency, C
L
= Output Load Capacitance, V
CC
= Supply Voltage, f
o
= Output Frequency.
Timing Diagrams
CP
MR
TE
PE
PL
P0
P1
P2
P3
P4
P5
P6
P7
TC
HC/HCT40103 COUNT
255 254
3
2
1
0
255 254 254 253
8
7
6
5
4
255
254 253 252
FIGURE 2.
7

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CD74HC40103-Q1,CD74HC4015,CD74HC4017,CD74HC4020,CD74HC4040,CD74HC4046A,CD74HC4049

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