CD74HC40103, CD74HCT40103
Test Circuits and Waveforms
t
r
CP
90%
10%
t
W
1/f
MAX
t
f
INPUT LEVEL
V
S
GND
MR
V
S
t
W
INPUT LEVEL
GND
t
PHL
TC 10%
90%
t
THL
t
PLH
V
S
CP
t
TLH
t
REM
V
S
INPUT LEVEL
GND
FIGURE 3.
FIGURE 4.
t
f
10%
90%
t
PHL
TC
10%
90%
t
THL
V
S
t
f
INPUT LEVEL
MR
t
SU
CP
t
TLH
V
S
V
S
t
h
INPUT LEVEL
GND
INPUT LEVEL
GND
t
PLH
V
S
TE
FIGURE 5.
FIGURE 6.
VALID
INPUTS
V
S
P0 - P7
PE
t
SU
t
h
INPUT LEVEL
V
S
t
SU
CP
V
S
t
h
t
REC
GND
INPUT LEVEL
GND
INPUT LEVEL
GND
TE
OR
PE
CP
V
S
t
SU
t
h
V
S
INPUT LEVEL
GND
INPUT LEVEL
GND
FIGURE 7.
I
t
WL
+ t
WH
=
fC
L
V
CC
50%
10%
t
WL
50%
50%
GND
t
WH
CLOCK
t
r
C
L
= 6ns
FIGURE 8.
t
WL
+ t
WH
=
t
f
C
L
= 6ns
2.7V
0.3V
I
fC
L
3V
1.3V
0.3V
t
WL
1.3V
1.3V
GND
t
WH
t
r
C
L
CLOCK
90%
10%
t
f
C
L
NOTE: Outputs should be switching from 10% V
CC
to 90% V
CC
in
accordance with device truth table. For f
MAX
, input duty cycle = 50%.
FIGURE 9. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
NOTE: Outputs should be switching from 10% V
CC
to 90% V
CC
in
accordance with device truth table. For f
MAX
, input duty cycle = 50%.
FIGURE 10. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
8