您的位置：维库电子市场网 > Datasheet > ISL5416

ISL5416 Datasheet

  • ISL5416

  • Four-Channel Wideband Programmable DownConverter

  • 2008.00KB

  • 71页

  • INTERSIL   INTERSIL

阅览下载 纠错 0

扫码查看芯片数据手册

上传产品规格书

PDF预览

ISL5416
Tables of Top Level Registers
In the tables below 鈥渞eset state鈥?indicates the register
contents after a HW reset or a SW hard reset. Unless
noted, a soft channel reset does not clear register
contents. A soft channel reset does clear the slave
registers of a master/slave pair (such as channel data
path control) but does not clear the master.
This register controls the output SYNC signal polarity, the
output clock rate and polarity, output data modes, and
channel cascading.
TABLE 15. COMMON OUTPUT CONTROL FUNCTIONS (GWA = 0000h)
RESET STATE = 0x00000001h
P(31:0)
31
FUNCTION
ENABLE SERIAL OUTPUT.
1 = serial output mode is enabled. The DOUT parallel data bus is replaced with 4 serial output busses -- one per channel. See 0*06h
- 0*08h and Table 30.
RESERVED. Set to 0.
SCLK RESET.
1 = serial clock divider is reset by SYNCInX if the reset serial output bit is set in IWA = *000h, bits 13 or 29 of any of the 4 channels.
SCLK POLARITY.
1 = Low to High transitions at the center of the data bit.
0 = High to Low transitions at the center of the data bit.
SCLK RATE.
000 = SCLK DIsabled.
001 = input clock rate.
010 = input clock rate / 2.
011 = input clock rate / 4.
100 = input clock rate / 8.
101 = input clock rate /16.
RESERVED. Set to 0.
ROUTE CHANNEL 2 TO CHANNEL 3.
1 = route the output of FIR2 of channel 2 to the input of the CIC to FIR1 gain block in channel 3.
ROUTE CHANNEL 1 TO CHANNEL 2.
1 = route the output of FIR2 of channel 1 to the input of the CIC to FIR1 gain block in channel 2.
ROUTE CHANNEL 0 TO CHANNEL 1.
1 = route the output of FIR2 of channel 0 to the input of the CIC to FIR1 gain block in channel 1.
CHANNEL 0 EXTERNAL AGC SOURCE SELECT.
0 = when bit 14 is set, Channel 1 controls Channel 0 gain.
1 = when bit 14 is set, Channel 3 controls Channel 0 gain.
CHANNEL 2 EXTERNAL/INTERNAL GAIN CONTROL.
1 = Channel 2 gain is controlled by Channel 3.
CHANNEL 1 EXTERNAL/INTERNAL GAIN CONTROL.
1 = Channel 1 gain is controlled by Channel 3.
CHANNEL 0 EXTERNAL/INTERNAL GAIN CONTROL.
1 = Channel 0 gain is controlled by Channel 3 or Channel 1 depending on the state of bit 17.
CLKO2 OR INTRPT.
1 = CLKO2/INTRPT is INTRPT (2 clock period wide pulse).
0 = CLKO2/INTRPT is CLKO2.
NOTE: For INTRPT IWA = 0*0Ah, bit 31 must be set for the channel that is the interrupt source..
FSYNCX POLARITY.
0 = active high
1 = active low.
30
29
28
27:25
24:21
20
19
18
17
16
15
14
13
12
32

ISL5416 PDF文件相关型号

ISL5416KI

ISL5416相关型号PDF文件下载

您可能感兴趣的PDF文件资料

热门IC型号推荐

©2024 维库电子市场网（www.dzsc.com）　备案号：浙B2-20050339-1 经营许可证：浙B2-20210386版权声明
买家服务热线：0571-85317607 | 买家服务部QQ： QQ:1609526468
卖家服务热线：0571-85317607 | 卖家服务部QQ： QQ:331652727

扫码下载APP，
一键连接广大的电子世界。

在线人工客服

买家服务：
卖家服务：

0571-85317607

客服在线时间周一至周五
9:00-17:30

关注官方微信号，
第一时间获取资讯。

建议反馈
返回顶部

建议反馈

联系人：

联系方式：

按住滑块，拖拽到最右边
>>
感谢您向阿库提出的宝贵意见，您的参与是维库提升服务的动力！意见一经采纳，将有感恩红包奉上哦！

PDF纠错X

投诉电话：0571-85317607 投诉QQ：

如选匿名将无法为您反馈投诉结果，建议实名投诉！