ISL5416 Datasheet

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ISL5416

Pin Descriptions

NAME

TYPE

INTERNAL

PULL-UP/DOWN

DESCRIPTION

POWER SUPPLY

Vcc

VccIO

GND

INPUTS

Ain(16:0)

I

PULL DOWN

Parallel Data Input bus A. Sampled on the rising or falling edge (programmable) of clock when ENIA

is active (low). The bus order can be programmed (See IWA = 0*00h, bit 4).

Parallel Data Input bus B. Sampled on the rising or falling edge (programmable) of clock when ENIB

is active (low). The bus order can be programmed (See IWA = 0*00h, bit 4).

Parallel Data Input bus C. Sampled on the rising or falling edge (programmable) of clock when ENIC

is active (low). The bus order can be programmed (See IWA = 0*00h, bit 4).

Parallel Data Input bus D. Sampled on the rising or falling edge (programmable) of clock when ENID

is active (low). The bus order can be programmed (See IWA = 0*00h, bit 4).

Input enable for Parallel Data Input bus A. Active low. This pin enables the input to the part in one of

two modes, gated or interpolated. In gated mode, one sample is taken per CLK when ENIx is

asserted.

Input enable for Parallel Data Input bus B. Active low. This pin enables the input to the part in one of

two modes, gated or interpolated. In gated mode, one sample is taken per CLK when ENIx is

asserted.

Input enable for Parallel Data Input bus C. Active low. This pin enables the input to the part in one of

two modes, gated or interpolated. In gated mode, one sample is taken per CLK when ENIx is

asserted.

Input enable for Parallel Data Input bus D. Active low. This pin enables the input to the part in one of

two modes, gated or interpolated. In gated mode, one sample is taken per CLK when ENIx is

asserted.

-

-

-

Positive Power Supply Voltage (core), 1.8V

卤0.09

Positive Power Supply Voltage (I/O), 3.3V

卤0.165

Ground, 0V.

Bin(16:0)

I

PULL DOWN

Cin(16:0)

I

PULL DOWN

Din(16:0)

I

PULL DOWN

ENIA

I

PULL DOWN

ENIB

I

PULL DOWN

ENIC

I

PULL DOWN

ENID

I

PULL DOWN

CONTROL

CLKA

CLKB

CLKC

CLKD

SYNCIn1

I

I

I

I

I

PULL DOWN

PULL DOWN

PULL DOWN

PULL DOWN

Input clock for data bus A. CLKA or CLKC may be used for Ain(16:0).

Input clock for data bus B. CLKB or CLKC may be used for Bin(16:0).

Input clock for data bus C. CLKC is also the master clock for all channels of ISL5416

Input clock for data bus D. CLKD or CLKC may be used for Din(16:0).

Global synchronization input signal 1. SYNCIn1 can update the carrier NCOs, reset decimation

counters, restart the filter, and restart the output section among other functions. For most of the

functional blocks, the response to SYNCIn1 is programmable and can be enabled or disabled.

Global synchronization input signal 2. SYNCIn2 can update the carrier NCOs, reset decimation

counters, restart the filter, and restart the output section among other functions. For most of the

functional blocks, the response to SYNCIn2 is programmable and can be enabled or disabled.

Synchronization Output Signal. The processing of multiple ISL5416 devices can be synchronized by

tying the SYNCO from one ISL5416 device (the master) to the SYNCIn of all the ISL5416 devices

(the master and slaves). An optional internal SYNCO to SYNCInX connection is provided.

PULL UP

Reset Signal. Active low. Asserting reset will halt all processing and set certain registers to default

values.

SYNCIn2

I

PULL DOWN

SYNCO

O

RESET

I

4

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