ISL5416 Datasheet

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ISL5416

Electrical Specifications

DSTRB Enable Time

DSTRB Disable Time (Note 6)

CE Setup Time to Falling Edge of DSTRB

CE Hold Time from Rising Edge of DSTRB (Note 7)

DSTRB Low Time

READ Cycle Time (Note 8)

JTAG TIMING (FIGURE 17)

TDI, TMS Set Up

TDI, TMS Hold

TCLK TO TDO VALID

TCLK TO TDO DISABLED

TCLK TO TDO ENABLED

CAPTURE INPUT SETUP TIME

CAPTURE INPUT HOLD TIME

TCLK TO OUTPUT VALID (Note 6)

CLOCK OUTPUT TIMING AND OUTPUT ENABLES (FIGURE 18)

CLKC to Parallel Data, FSYNCX and CLKO1 (Divide-by 2 thru 16 Modes)

CLKC Low to CLKO1 Low (Divide-by 1 Mode)

CLKC High to CLKO1 High (Divide-by 1 Mode)

Time Skew Between CLKO1 and Parallel Data or FSYNCX (Divide-by 2 thru 16 Modes)

Time Skew Between CLKO1 and Parallel Data or FSYNCX (Divide-by 1 Mode)

OUTPUT ENABLE TIME

OUTPUT DISABLE TIME

NOTES:

5. The ISL5416 goes into reset immediately on RESET going low and comes out of reset on the 4th rising edge of CLK after RESET goes high.

6. Controlled via design or process parameters and not directly tested. Characterized upon initial design and at major process or design changes.

7. t

AHR

and t

CHR

apply ONLY to direct reads of addresses 4 - 7.

8. Reading from direct addresses 4 - 7 (Sequential Read Mode).

t

PD

t

PDL

t

PDH

t

SKEW3

t

SKEW4

t

OEN

t

ODIS

2

(NOTE 6)

2

(NOTE 6)

2

(NOTE 6)

-1.5

-2.5

6.5

6.5

6.5

1.5

1.5

6

4

ns

ns

ns

ns

ns

ns

ns

TS

TT

TH

TT

TOV

TDO

TOD

TDO

TOE

TDO

t

ISTP

t

IHLD

t

DVLD

5

1.5

2

6

4.5

1.5

7

7

7

ns

ns

ns

ns

ns

ns

ns

ns

V

CCC

= Core supply: 1.8V

卤

0.09V, V

CCIO

= IO鈥檚 supply: 3.3V

卤

0.165V, T

A

= -40 C to 85 C Industrial

PARAMETER

SYMBOL

t

RE

t

RD

t

CSF

t

CHR

t

DW

t

RCY

MIN

-

-

7.5

-2

5

25

MAX

14

6.5

-

-

-

UNITS

ns

ns

ns

ns

ns

ns

o

o

AC Test Load Circuit

DUT

S

1

C

L

(NOTE)

NOTE - TEST HEAD CAPACITANCE, 50pF (TYP)

SWITCH S1 OPEN FOR I

CCSB

AND I

CCOP

I

OH

卤

1.5V

I

OL

EQUIVALENT CIRCUIT

59

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