您的位置：维库电子市场网 > Datasheet > AD7763

AD7763 Datasheet

  • AD7763

  • 24-Bit, 625 kSPS, 109 dB Σ-Δ ADC with On-Chip Buffers, Ser...

  • 1652.00KB

  • 34页

  • AD

阅览下载 纠错 0

扫码查看芯片数据手册

上传产品规格书

PDF预览

AD7763
Pin No.
17
37
3
2
36
38
39, 40, 45
Mnemonic
R
BIAS
RESET
MCLK
MCLKGND
SYNC
DRDY
SH2:0
Description
Bias Current Setting. A resistor must be inserted between this pin and AGND.
See the Bias Resistor Selection section.
A falling edge on this pin resets all internal digital circuitry. Holding this pin low
keeps the AD7763 in a reset state.
Master Clock Input. A low jitter digital clock must be applied to this pin. The output data rate
depends on the frequency of this clock. See the Clocking the AD7763 section.
Master Clock Ground Sensing Pin.
Synchronization Input. A falling edge on this pin resets the internal filter. This can be used
to synchronize multiple devices in a system.
Data Ready Output. Each time new conversion data is available, an active low pulse,
锟?frac12; ICLK period wide, is produced on this pin. See the AD7763 Interface section.
Share Pins 2:0. For multiple AD7763 devices sharing a common serial bus. Each device is wired
with the binary value that represents the number of devices sharing the serial bus. SH2 is the
MSB. See the Sharing the Serial Bus section.
Address 2:0. Allows multiple AD7763 devices to share a common serial bus. Each device must be
programmed with an individual address using these three pins. See the Sharing the Serial Bus
section.
Serial Clock Polarity. Determines on which edge of SCO the data bits are clocked out and on
which edge they are valid. All timing diagrams are shown with SCP = 0, and all SCO edges
shown should be inverted for SCP = 1.
Serial Data Latch. A pulse is output on this pin after every 16 data bits. The pulse is one SCO
period wide and can be used in conjunction with FSO as an alternative framing method for
serial transfers requiring a framing signal more frequent than every 32 bits.
Frame Sync In. The status of this pin is checked on the falling edge of SCO. If this pin is low, then
the first data bit is latched in on the next SCO falling edge when SCP = 0 or on the rising edge of
SCO if SCP = 1.
Serial Data In. The first data bit (MSB) must be valid on the next SCO falling edge when SCP = 0
(or SCO rising edge SCP = 1) after the FSI event has been latched. Each write requires 32 bits: the
ALL bit, 3 address bits, and 12 register address bits, followed by the remaining 16 bits of data to
be written to the device.
Serial Data Out. Address, status, and data bits are clocked out on this line during each serial
transfer.
If SCP = 0, each bit is clocked out on an SCO rising edge and is valid on the falling edge. When
the I
2
S pin is set to logic high, this pin outputs the signal defined as SD in the I
2
S bus
specification. See the Reading Data Using the I
2
S Interface section for details.
Serial Clock Out. This clock signal is derived from the internal ICLK signal. The frequency of SCO
is equal to either ICLK or ICLK/2, depending on the state of the CDIV and SCR pins (see the
AD7763 Interface section). When the I
2
S pin is logic high, this pin outputs the signal defined as
SCK by the I
2
S bus specification. See the Reading Data Using the I
2
S Interface section.
Frame Sync Out. This signal frames the serial data output and is 32 SCO periods wide. The
exception to the framing behavior of FSO occurs in decimate 脳 32 mode, where, for certain
combinations of CDIV and SCR, the FSO signal is constantly logic low. See the Reading Data
Using the SPI Interface section. When the I
2
S pin is set to logic high, this pin outputs the signal
defined as WS in the I
2
S bus specification. See the Reading Data Using the I
2
S Interface section.
Clock Divider. This pin is used to select the ratio of MCLK to ICLK. See the AD7763 Interface
section.
Serial Clock Rate. This pin and the CDIV pin program the SCO frequency (see Table 7).
I
2
S Select. A Logic 1 on this pin changes the serial data-out mode from SPI to I
2
S. The SDO pin
outputs as the SD signal, the SCO pin outputs the SCK signal, and the FSO pin outputs the WS
signal. When writing to the AD7763, the I
2
S pin is set to logic low and the SPI interface is used.
See the Reading Data Using the I
2
S Interface section for further details.
46 to 48
ADR2:0
49
SCP
50
SDL
51
FSI
52
SDI
54
SDO
55
SCO
56
FSO
58
60
61
CDIV
SCR
I
2
S
Rev. 0 | Page 9 of 32

AD7763相关型号PDF文件下载

您可能感兴趣的PDF文件资料

热门IC型号推荐

©2026 维库电子市场网（www.dzsc.com）　备案号：浙B2-20050339-1 经营许可证：浙B2-20210386版权声明
买家服务热线：0571-85317607 | 买家服务部QQ： QQ:1609526468
卖家服务热线：0571-85317607 | 卖家服务部QQ： QQ:331652727

扫码下载APP，
一键连接广大的电子世界。

在线人工客服

买家服务：
卖家服务：
技术客服：

0571-85317607

网站技术支持

13606545031

客服在线时间周一至周五
9:00-17:30

关注官方微信号，
第一时间获取资讯。

建议反馈
返回顶部

建议反馈

联系人：

联系方式：

按住滑块，拖拽到最右边
>>
感谢您向阿库提出的宝贵意见，您的参与是维库提升服务的动力！意见一经采纳，将有感恩红包奉上哦！

PDF纠错X

投诉电话：0571-85317607 投诉QQ：

如选匿名将无法为您反馈投诉结果，建议实名投诉！